Flexible Command Addressing for Memory Pin Reduction
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Solution Overview
Problem
3D stacked memory devices require a large number of bus connections for row and column commands, leading to increased pin requirements and complexity, which can be inefficient and costly.
Innovation Solution
Implementing a flexible command addressing system that uses a shared bus for both row and column commands, eliminating the need for dedicated pins by utilizing a shared bus mode that interprets signals for both command types on common pins, allowing for reduced pin usage and improved command efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated pins are used for row and column commands in stacked memory, then command reliability is improved, but device complexity and pin requirements increase
Solution Approach 1:
The patent applies universality by enabling common pins to serve dual purposes: they can be configured to carry either row commands or column commands based on control signals. The memory device includes logic that interprets command type based on pin configuration, allowing the same physical pins to universally handle different command types without requiring dedicated pins for each function.
Solution Approach 2:
The patent implements dynamics through configurable pin assignment where the function of pins is not fixed but can be dynamically changed via control signals. The memory device can switch between different pin configurations to accommodate different command types, making the pin assignment flexible and adaptable rather than static and dedicated.
2Measurement precision
If separate bus connections are provided for row and column commands, then command interpretation accuracy is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent applies universality by designing a shared bus structure where common pins can be configured to carry different command types. The memory device includes interpretation logic that determines command type based on control signals, allowing a single bus structure to universally handle both row and column commands without requiring separate dedicated buses for each command type.
Solution Approach 2:
The patent implements parameter changes by using control signals to dynamically change the interpretation parameters of the shared bus. The memory device adjusts its command interpretation behavior based on the state of control signals, allowing the same physical bus to be interpreted differently for row versus column commands, thereby maintaining accuracy without requiring separate physical buses.
3Reliability
If multiple bus connections are used for stacked memory channels, then command reliability is improved, but the number of pin connections and device complexity increase
Solution Approach 1:
The patent applies merging by combining the row command bus and column command bus into a single shared bus structure. Instead of providing separate physical connections for row and column commands, the patent merges these functions into common pins that can be configured to carry either type of command, thereby reducing the total number of pin connections while maintaining reliable command transmission.
Solution Approach 2:
The patent applies universality by enabling the shared bus to serve multiple functions: it can carry row commands when configured one way and column commands when configured another way. This multi-functional design allows a single bus structure to replace what would traditionally require separate dedicated buses, reducing pin count while maintaining command reliability through proper signal interpretation.
Data Source
AI summary
Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.