Flexible Data Bus Protocol for Microprocessor Interface
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Solution Overview
Problem
Conventional microprocessor data bus configurations require a large number of pins and excessive power for data transactions, which is problematic in applications with size and power constraints, while also lacking flexibility in data transfer modes.
Innovation Solution
A microprocessor with data bus configuration logic that enables either full-width or half-width data transactions, reducing the number of data signal group pins and power consumption by performing doubleword transfers in half-width mode and quadword transfers in full-width mode, with mode negotiation between devices on the system bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional full-width data bus configuration is used, then data transfer speed is improved, but package size and power consumption increase
Solution Approach 1:
The data bus interface is made dynamically configurable between full-width and half-width modes through mode negotiation logic. The system can switch between operating modes based on transaction requirements, allowing the data bus width to be adjusted dynamically rather than being fixed, thus resolving the contradiction between speed and package size.
Solution Approach 2:
The invention changes the parameter of data bus width from a fixed full-width configuration to a variable parameter that can be set to either full-width or half-width mode. This parameter change allows the system to optimize between data transfer speed and package size/power consumption by selecting the appropriate width based on transaction needs.
2Productivity
If conventional full-width data bus configuration is used, then data transfer capability is improved, but power consumption increases
Solution Approach 1:
The power consumption issue is resolved by making the data bus operation dynamic - the system negotiates and switches between full-width and half-width modes based on actual transaction requirements. When full data transfer capability is needed, full-width mode is used; when lower bandwidth suffices, half-width mode reduces power consumption significantly.
Solution Approach 2:
By changing the data bus width parameter between full and half width, the system can adjust power consumption levels while maintaining adequate data transfer capability for different application scenarios, directly addressing the contradiction between productivity and energy use.
3Speed
If fixed full-width data bus mode is used, then maximum data transfer rate is achieved, but flexibility for varying applications is reduced
Solution Approach 1:
The data bus interface is designed with multi-functionality through mode negotiation capability. The same physical data bus infrastructure can operate in both full-width mode for high-performance applications and half-width mode for power-constrained or lower-bandwidth applications, making the system universally adaptable to varying application requirements without sacrificing maximum transfer rate capability when needed.
Data Source
AI summary
A microprocessor interface system including a system bus with a bus clock and a data signal group in which multiple devices are coupled to the system bus. Each device is configured to perform a half-width data transaction on the system bus in which a doubleword is transferred for each of four beats during each of four consecutive cycles of the bus clock. The data signal group may include multiple data strobes, such as first and second data strobes for latching first and third doublewords and third and fourth data strobes for latching second and fourth doublewords during each cycle of the bus clock. Each doubleword may be provided on first and second data portions of the data signal group. The first and second data strobes may latch data on the first data portion and the third and fourth data strobes may latch data on the second data portion.