Flexible Data Pin Configuration for Memory Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing memory devices, such as DRAM chips, require an additional redistribution layer (RDL) to connect data pins with package pins when their configurations differ, leading to increased manufacturing costs, power consumption, and occupied space.
Innovation Solution
Incorporating a memory device with data pins configured in a second bit order and package pins in a first bit order, along with switches that perform swapping operations to align data bit orders, eliminating the need for a redistribution layer by ensuring compatibility without additional layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an additional redistribution layer is used to connect data pins to package pins with different configurations, then compatibility between data pins and package pins is improved, but manufacturing cost increases, power consumption increases, and occupied space increases
Solution Approach 1:
The patent implements dynamic configuration of data pin bit orders through control signals that can switch between first bit order and second bit order. This dynamic adaptability allows the memory device to match different package pin configurations without requiring additional redistribution layers, thereby reducing manufacturing complexity while maintaining compatibility.
Solution Approach 2:
The patent changes the bit order parameter of data pins from fixed to variable. By allowing data pins to operate in different bit order configurations (first bit order or second bit order), the system can adapt to various package pin arrangements without adding physical redistribution layers, thus reducing manufacturing cost and device complexity.
2Adaptability or versatility
If an additional redistribution layer is used to connect data pins to package pins with different configurations, then compatibility between data pins and package pins is improved, but power consumption increases
Solution Approach 1:
The dynamic bit order configuration eliminates the need for additional redistribution layers, reducing the number of signal paths and associated power consumption. The control signals that switch bit orders enable the system to optimize power usage by directly connecting data pins to matching package pins without extra routing through redistribution layers.
Solution Approach 2:
By changing the bit order parameter of data pins, the system achieves compatibility with different package pin configurations through logical reconfiguration rather than physical redistribution. This parameter-based adaptation reduces the number of active signal paths and associated power consumption compared to using additional redistribution layers.
3Adaptability or versatility
If an additional redistribution layer is used to connect data pins to package pins with different configurations, then compatibility between data pins and package pins is improved, but occupied space of the package increases
Solution Approach 1:
The dynamic bit order switching capability allows the memory device to adapt to different package pin configurations without requiring additional physical space for redistribution layers. By changing the logical configuration of data pins rather than adding physical routing layers, the package footprint is minimized while maintaining compatibility.
Solution Approach 2:
The patent uses parameter-based adaptation (changing bit order) instead of adding physical redistribution layers. This approach achieves compatibility with various package pin configurations without increasing the occupied space of the package, as the reconfiguration is achieved through control signals rather than additional physical structures.
Data Source
AI summary
A memory device includes at least one memory bank, a plurality of data pins coupled to a plurality of package pins, a data input/output (IO) circuit, at least one bank IO circuit and a plurality of switches. The package pins correspond to a first bit order, and the data pins correspond to a second bit order. The data IO circuit is configured to communicate a first data with the data pins, wherein the first data is arranged in the first bit order. The bank IO circuit is configured to communicate a second data with the memory bank, wherein the second data is arranged in the second bit order. The plurality of switches perform at least one swapping operation on the first data to generate the second data or to perform the at least one swapping operation on the second data to generate the first data.