Flexible Data Rate Handling in CAN Bus Receiver Circuit
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Solution Overview
Problem
Existing CAN bus systems face challenges in reducing power consumption, especially when handling flexible data rate messages, and may incorrectly detect frames, leading to unnecessary wake-ups and increased power consumption, particularly under low-power and low-clock accuracy conditions.
Innovation Solution
A receiver circuit with a flexible data rate detector and a recessive bit counter that activates an analog filter only when a Flexible Data Rate Format bit is detected, allowing for efficient detection of the end of a flexible data rate frame using a low-power, low-precision RC oscillator, and avoiding false error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the receiver monitors and analyzes the bit stream under severe power limitations, then power consumption is reduced, but clock accuracy is limited and error detection may occur
Solution Approach 1:
The system dynamically switches between two operational modes: low-power monitoring mode and full-power processing mode. The receiver circuit transitions from passive bit stream monitoring to active frame processing based on detection of the FDF bit, optimizing power consumption while maintaining accuracy when needed
Solution Approach 2:
The system changes operational parameters (power state, processing intensity) based on the detected message type. When a flexible data rate frame is detected via the FDF bit, the system activates full processing with accurate clocking; otherwise, it maintains low-power monitoring, thus adapting parameters to match actual requirements
2Measurement precision
If the receiver processes flexible data rate frames with high data rate, then accurate frame detection is achieved, but power consumption increases
Solution Approach 1:
The reception process is segmented into distinct phases: initial low-power monitoring phase, detection phase (identifying FDF bit), and processing phase (activated only for FD frames). This segmentation allows the system to spend most time in low-power state while maintaining capability for high-accuracy processing when required
Solution Approach 2:
The system performs partial processing by only fully processing frames that are identified as flexible data rate frames through the FDF bit detection. Non-FD frames receive minimal processing, avoiding unnecessary high-power consumption while maintaining adequate functionality
3Use of energy by moving object
If the receiver uses low-power mode with limited clock accuracy, then power consumption is reduced, but false error detection occurs leading to unnecessary wake-ups
Solution Approach 1:
The system performs preliminary detection of the FDF bit in low-power mode before committing to full frame processing. This preliminary action allows the receiver to identify flexible data rate frames early and activate full processing only when necessary, preventing false errors by ensuring proper processing mode is used
Solution Approach 2:
The FDF bit detection acts as an intermediary mechanism that bridges low-power monitoring and high-power processing. This intermediary allows the system to make informed decisions about power state transitions, ensuring that full processing is activated only when actually needed, thus avoiding false error detections
Data Source
AI summary
The present invention relates to a receiver circuit for processing an incoming bit stream from a bus system. The circuit comprises an analog interface for converting the analog signal to a digital input data stream. The interface comprises an analog filter and a switch to process the analog signal before generating the digital input data stream using the filter if, and only if, a selection criterion controlling the switch is met. The circuit comprises a frame decoding unit for decoding a data frame encoded in the digital input data stream in accordance with a CAN protocol, and a frame processing unit that comprises a flexible data rate detector and a recessive bit counter for counting consecutive recessive bits after detecting the flexible data rate frame. The selection criterion is satisfied when the flexible data rate frame is detected and unsatisfied when the recessive bit counter reaches a predetermined number.