Flexible Decoupling Capacitor Fill Design for IC Density
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Solution Overview
Problem
Traditional decoupling capacitor designs in integrated circuits are inflexible and inefficient, particularly as integrated circuit density increases, making it difficult to achieve desired sizes and locations due to restrictions from power grid channels and underlying metal layers, which limits the placement of decoupling capacitors.
Innovation Solution
A flexible approach to designing and placing decoupling capacitors by identifying eligible areas for smaller decap cells with built-in power tracks that can be connected to power grids, allowing for butting together of cells in horizontal or vertical arrays, independent of the power grid pitch, and placement in any area with sufficient space, reducing interference from other design parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional linear dcap fill along power grid channels is used, then dcap placement is constrained to channel areas, but this eliminates many potential placement areas and reduces dcap density as circuit density increases
Solution Approach 1:
The decoupling capacitor is divided into multiple separate capacitor fingers or segments that can be distributed across different locations in the circuit. Instead of placing one large dcap along the power grid channel, multiple smaller capacitor segments are placed in various eligible areas, increasing overall placement flexibility and density while maintaining the required total capacitance value.
Solution Approach 2:
The invention transitions from one-dimensional linear placement along power grid channels to two-dimensional distributed placement across the entire circuit layout. Capacitor segments can be positioned in any eligible area regardless of power grid channel location, utilizing unused spaces and increasing placement freedom in both horizontal and vertical dimensions.
2Quantity of substance
If dcap size is increased to achieve desired capacitance, then fewer dcaps are needed, but larger dcaps are more difficult to place in high-density circuits and may block routing channels
Solution Approach 1:
The total capacitance requirement is segmented into multiple smaller capacitor units distributed throughout the circuit. Each segment is small enough to fit in available spaces without blocking routing channels, while the cumulative effect of all segments achieves the desired total capacitance value for power supply decoupling.
Solution Approach 2:
Instead of placing a few large capacitors that might block routing, the invention uses multiple smaller capacitors distributed throughout the circuit. This partial distribution approach ensures that each individual capacitor is small enough not to interfere with routing while collectively providing sufficient decoupling capacitance.
3Ease of manufacture
If dcap placement follows power grid channels, then connection to power rails is simplified, but design objects on underlying metal layers block dcap placement and create design rule violations
Solution Approach 1:
The invention moves capacitor placement from the constrained one-dimensional power grid channel space to two-dimensional areas throughout the circuit layout. Capacitor segments can be placed in eligible areas regardless of their proximity to power grid channels, utilizing spaces above or below power grid channels that would otherwise be unavailable for placement.
4Productivity
If routing is performed before dcap placement, then routing channels are established, but routed wires block areas needed for dcap placement
Solution Approach 1:
The capacitor is segmented into multiple small fingers or units that can be distributed throughout the circuit. These small segments can be placed in available spaces between routed wires and other design objects, allowing routing to be completed first without significantly impacting subsequent capacitor placement flexibility.
Solution Approach 2:
Instead of requiring large continuous areas for capacitor placement, the invention uses multiple small capacitor segments distributed throughout the circuit. This allows capacitor placement to proceed even after routing is complete, as the small segments can fit in the gaps and spaces created by the routed wires.
Data Source
AI summary
A method of filling dcaps in an integrated circuit includes identifying a set of dcap-eligible areas of the integrated circuit for areas large enough to accommodate at least one dcap cell having a selected size smaller than a default size. The dcap cell includes at least one built-in power track. A set of dcap cells are filled in the identified set of dcap-eligible areas. Each of the built-in power tracks included in the set of dcap cells is connected to a corresponding power grid. An integrated circuit including a power grid channel formed between at least two power grids and a plurality of dcaps including a first dcap included in a dcap cell, the dcap cell including built-in power tracks, each one of the built-in power tracks being connected to a corresponding one of the at least two power grids is also described.