Flexible DSP Circuit for FIR Filtering Without Pre-Adders

Solution Overview

Problem

In deep submicron integrated circuits, pre-adders required for arithmetic operations consume valuable die area and power due to the need for a register stage between adders and multipliers, limiting area efficiency and increasing latency in digital signal processing blocks like FIR filters.

Innovation Solution

Replacing pre-adders with additional multipliers in digital signal processing blocks allows for the same arithmetic operations with reduced area usage and lower latency, enabling efficient implementation of both real and complex multiplications, and supporting symmetric FIR filtering without the need for register stages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If pre-adders are used in digital signal processing blocks, then arithmetic operations can be performed, but die area and power consumption increase due to the required register stage

Engineering Contradiction:

Improvearithmetic operation capabilityVSAvoiddie area

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent merges the pre-adder functionality with the multiplier by sharing the adder circuit between the pre-adder stage and the final accumulation stage. This consolidation eliminates the need for a separate register stage between adders and multipliers, reducing die area while maintaining arithmetic operation capability in deep submicron integrated circuits

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The adder circuit is designed to serve multiple functions: it acts as both a pre-adder for symmetric FIR filter operations and as an accumulator for general-purpose arithmetic operations. This multi-functionality eliminates the need for dedicated pre-adder hardware, reducing die area consumption while preserving full arithmetic capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of manufacture

If pre-adders are used in digital signal processing blocks, then arithmetic operations can be performed, but power consumption increases due to the register stage

Engineering Contradiction:

Improvearithmetic operation capabilityVSAvoidpower consumption

Core Design Contradiction:

Ease of manufactureVSUse of energy by stationary object

Solution Approach 1:

The patent merges the pre-adder functionality with the multiplier by sharing the adder circuit between the pre-adder stage and the final accumulation stage. This consolidation eliminates the need for a separate register stage between adders and multipliers, reducing die area while maintaining arithmetic operation capability in deep submicron integrated circuits

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The adder circuit is designed to serve multiple functions: it acts as both a pre-adder for symmetric FIR filter operations and as an accumulator for general-purpose arithmetic operations. This multi-functionality eliminates the need for dedicated pre-adder hardware, reducing die area consumption while preserving full arithmetic capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Ease of manufacture

If pre-adders are used in digital signal processing blocks, then arithmetic operations can be performed, but latency increases due to the register stage

Engineering Contradiction:

Improvearithmetic operation capabilityVSAvoidlatency

Core Design Contradiction:

Ease of manufactureVSLoss of time

Solution Approach 1:

The patent merges the pre-adder functionality with the multiplier by sharing the adder circuit between the pre-adder stage and the final accumulation stage. This consolidation eliminates the need for a separate register stage between adders and multipliers, reducing die area while maintaining arithmetic operation capability in deep submicron integrated circuits

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The adder circuit is designed to serve multiple functions: it acts as both a pre-adder for symmetric FIR filter operations and as an accumulator for general-purpose arithmetic operations. This multi-functionality eliminates the need for dedicated pre-adder hardware, reducing die area consumption while preserving full arithmetic capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240113699A1Flexible Circuit for Real and Complex Filter Operations

Publication Date: 2024.04.04 ALTERA CORP

AI summary

Integrated circuit devices, methods, and circuitry for implementing and using a flexible circuit for real and complex filter operations are provided. An integrated circuit may include programmable logic circuitry and digital signal processor (DSP) blocks. The DSP blocks may be configurable to receive inputs from the programmable logic circuitry and may include first and second multiplier pairs. The first multiplier pair may include a first multiplier that may receive a first input and a second input and a second multiplier that may receive the second input and a third input of the inputs. The second multiplier pair may include a third multiplier that may receive the first input or a fourth input and a fifth input and a fourth multiplier that may receive the third input or a fifth input and a sixth input.