Flexible Error Correction Architecture for Semiconductor Memory
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Solution Overview
Problem
Existing semiconductor memory products face challenges in minimizing latency and chip size while providing error correction capabilities, as traditional error correction codes (ECC) increase latency and require significant circuit area, making them unsuitable for sensitive and safety-critical applications.
Innovation Solution
A flexible, low-latency error correction architecture that allows dynamic switching of ECC on and off, shares circuit components between neighboring memory regions, and reduces data bus loading, enabling minimal chip size overhead and improved performance with or without ECC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction codes (ECC) are used to correct errors in semiconductor memory devices, then reliability is improved, but latency increases and chip size overhead increases
Solution Approach 1:
The memory device is divided into multiple memory banks, each with dedicated ECC circuitry. This segmentation allows parallel error correction operations across different banks, reducing overall latency while maintaining comprehensive error correction coverage across the entire memory device.
Solution Approach 2:
ECC circuitry is integrated directly within each memory bank, performing error correction operations concurrently with memory access operations. This preliminary integration eliminates sequential processing delays and reduces the time penalty associated with traditional ECC implementation.
2Reliability
If traditional error correction codes (ECC) are used to correct errors in semiconductor memory devices, then reliability is improved, but circuit area increases
Solution Approach 1:
ECC circuitry is merged with memory bank circuitry, sharing common structural elements and resources. This integration eliminates redundant circuit components and reduces overall chip area while maintaining full error correction functionality across all memory banks.
Solution Approach 2:
The ECC circuitry is designed with multi-functionality, serving multiple error correction purposes across different memory banks. This universal design allows a single ECC module to handle error correction for multiple data words, reducing the total circuit area required compared to dedicated ECC circuits for each memory location.
3Speed
If ECC circuitry is integrated in each memory bank, then error correction speed is improved, but device complexity increases
Solution Approach 1:
Each memory bank is equipped with locally-integrated ECC circuitry tailored to its specific requirements. This local quality approach allows optimization of error correction speed for each bank while using standardized designs to control overall device complexity.
Solution Approach 2:
The ECC system implements dynamic error correction capabilities, where the error correction process adapts to the specific error conditions detected in each memory bank. This dynamic approach improves error correction speed by focusing computational resources only where errors are present, rather than processing all data uniformly.
Data Source
AI summary
A novel architecture provides many of the advantages of the array and datapath architecture of DRAM products that do not utilize ECC (error correction code) functionality, while simultaneously allowing the flexible deployment of ECC error correction as needed. Aspects of the disclosure enable the minimization of write and read latency typically introduced by the implementation of ECC error correction. Sharing of circuit components between neighboring memory regions is also introduced, which allows for a reduction in circuit area as well as a reduction in loading on speed-critical data bus wiring, which improves overall performance. A very fast single error correct (SEC) and double error detect (DED) read-out for real-time system-level awareness is also provided.