Flexible Fan-Out Packaging Structure for Stress-Free Chip Stacking
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Solution Overview
Problem
Conventional semiconductor packaging methods, such as MCP and PoP, face challenges in miniaturization due to increased packaging area in the XY direction and stress-related issues like chip cracking and warpage, which limit the integration and reliability of chip stacking and interconnection.
Innovation Solution
A packaging structure and manufacturing method utilizing flexible substrates with hard plate, winding, and fan-out regions, where flexible dielectric layers and copper clad laminates are used to create a multi-layer stack with copper pillars and wiring layers, allowing for flexible chip stacking and interconnection without stress-induced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are arranged in the XY direction on a substrate, then packaging function integration is improved, but packaging area increases
Solution Approach 1:
The patent transitions from two-dimensional XY arrangement to three-dimensional stacking by bending the flexible substrate to bring fan-out regions into contact with the hard plate region, enabling vertical integration of multiple chips and reducing the footprint area
2Area of stationary object
If chips are stacked in the Z direction using MCP or PoP technology, then packaging area in XY direction is reduced, but stress causes chip cracking and warpage
Solution Approach 1:
The patent changes the mechanical parameter of the substrate from rigid to flexible, allowing the substrate to bend and conform to stress conditions, thereby reducing stress concentration that causes chip cracking and warpage while maintaining compact packaging
Solution Approach 2:
The patent uses a composite structure combining flexible substrate material with hard plate regions and copper pillars to create a multi-layer stack that distributes stress evenly, preventing chip cracking and warpage while achieving compact packaging
3Adaptability or versatility
If BGA interconnection is used between packages, then electrical conduction and physical indication are achieved, but stress from CTE difference causes interconnection failure
Solution Approach 1:
The patent changes the substrate flexibility parameter to allow the flexible substrate to accommodate thermal expansion differences through bending, reducing stress on the BGA interconnection and preventing solder ball detachment
Solution Approach 2:
The flexible substrate acts as an intermediary that absorbs and distributes stress between packages with different CTEs, protecting the BGA interconnection from stress-induced failure while maintaining electrical conduction
Data Source
AI summary
A packaging structure includes multiple packaging units, and the packaging units include a hard plate region, a winding region, and a fan-out region. In the packaging structure, the hard plate region of the packaging unit is arranged in a stacked manner, some or all of the fan-out regions are packaged with a chip, and some or all of the fan-out regions packaged with a chip are stacked with the hard plate regions after being bent by the winding region. So designed, each fan-out region is individually packaged and then packaged by stacking with each other to achieve the interconnections between a chip and a chip, and between a chip and a substrate without interference between the packaging units.