Flexible Fuse Transmission for Memory Redundancy
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving high data reliability, high speed of memory access, low power consumption, and reduced chip size, particularly in effectively handling defective memory cells through redundancy mechanisms.
Innovation Solution
The implementation of a redundancy data loading/transmitting circuit that includes a fuse block and a redundancy latch block, utilizing fuse arrays to store defective addresses and control bits, which enables the shifting of pointers to load defective addresses without skipping, thereby enabling access to redundant memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a daisy chain configuration of flip-flop circuits is used to transmit addresses, then the relationship between pointers and fuse arrays is fixed, but the flexibility to handle different memory configurations is reduced
Solution Approach 1:
The patent introduces a flexible pointer structure where pointers can be dynamically repositioned within the daisy chain configuration. The pointer position is determined by control signals rather than being fixed, allowing the same physical structure to adapt to different memory configurations and defect patterns without changing the fundamental daisy chain architecture.
2Reliability
If redundancy decoders are added to handle defective cells, then data reliability is improved, but device complexity increases
Solution Approach 1:
The redundancy decoder circuit is designed to serve multiple functions: it can decode addresses for different types of defects (row defects, column defects, multiple defects), handle various memory configurations, and operate with different pointer positions. This multi-functionality reduces the need for separate dedicated circuits for each defect type, thereby limiting the increase in device complexity while maintaining high reliability.
3Adaptability or versatility
If fuse arrays with multiple fuses are used to store defective addresses, then the capacity to handle defective cells is increased, but the chip size increases
Solution Approach 1:
The patent implements a nested structure where multiple fuse arrays are organized within a compact decoder architecture. The fuses are arranged in a hierarchical manner with shared decoding logic, allowing multiple defect addresses to be stored and managed within a space-efficient structure that minimizes the overall chip area while maintaining high capacity for handling defective cells.
Data Source
AI summary
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.