Flexible Hardware Engines for Multidimensional Vectors
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Solution Overview
Problem
Conventional processors are inefficient in exploiting parallelism and optimizing data paths and memory bandwidth for computer vision tasks, limiting their performance and flexibility in handling multidimensional vectors.
Innovation Solution
A coprocessor architecture with a scheduler circuit and hardware engines that parse and schedule directed acyclic graphs to execute multidimensional vector operations, optimizing internal and external memory bandwidth and supporting variable-size vectors, enabling efficient execution of computer vision tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional general purpose programmable processors are used with aggressive pipelining and out-of-order execution, then parallelism extraction is improved, but the implementation becomes inefficient and difficult for compilers to extract inherent parallelism
Solution Approach 1:
The processor is segmented into multiple specialized execution engines (vector processing engine, matrix processing engine, tensor processing engine) that can operate in parallel. Each engine is dedicated to specific types of operations, allowing the system to extract parallelism more efficiently without the complexity of general-purpose out-of-order execution.
Solution Approach 2:
The processor implements a unified architecture that can execute multiple types of operations (vector, matrix, tensor) across different domains. The scheduler and memory management units coordinate these diverse engines, providing universal functionality while maintaining efficiency for each specific operation type.
2Use of energy by moving object
If specialized engines are used for computer vision tasks, then power and cost efficiency is improved, but flexibility to support new or enhanced tasks is reduced
Solution Approach 1:
The processor implements dynamic configuration capabilities where the scheduler can allocate and reconfigure execution engines based on the specific task requirements. The memory management units can dynamically adjust bandwidth allocation, and the architecture supports loading different kernel modules to handle new or enhanced computer vision tasks while maintaining power efficiency.
Solution Approach 2:
The processor allows parameter changes in the execution engines through software control, enabling the same hardware to adapt to different computational patterns. The vector, matrix, and tensor engines can have their operational parameters adjusted to match the specific requirements of different computer vision algorithms, providing both efficiency and flexibility.
3Adaptability or versatility
If multidimensional vectors with variable dimensions are supported, then adaptability to different computer vision tasks is improved, but hardware engine complexity increases
Solution Approach 1:
The processor explicitly supports multidimensional vectors by adding dimensionality awareness to the execution engines. The vector, matrix, and tensor engines can operate on data with 0 to N dimensions, with the scheduler automatically managing the dimensional transformations. This allows adaptability to different computer vision tasks without requiring separate hardware for each dimensionality.
Data Source
AI summary
An apparatus includes a scheduler circuit and a processing circuit. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more operators and (ii) schedule the one or more operators in one or more data paths. The processing circuit generally comprises one or more hardware engines configured as the one or more data paths. The one or more hardware engines are generally configured to generate one or more output vectors in response to zero or more input vectors using the operators. At least one of the one or more hardware engines may support input vector dimensions ranging from zero to at least four dimensions. At least one of the one or more hardware engines is implemented solely in hardware.