Flexible Host Memory Buffer for SSD Caching

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Solution Overview

Problem

Conventional solid state drive (SSD) designs face limitations due to low memory capacity of SRAM caches and high memory density requirements of flash caches, which increase die size and cost, and impose constraints on power consumption and endurance, necessitating a more efficient caching solution that balances SSD and host performance.

Innovation Solution

Implementing a flexible host memory buffer system that allocates and dynamically manages host DRAM for SSD caching across a host bus, allowing the host to cache SSD data and metadata, thereby reducing the need for on-board DRAM and optimizing cache size based on workload analysis to balance performance and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If SRAM is used for L1 cache to improve access speed, then access time is reduced, but memory capacity and die size increase

Engineering Contradiction:

Improveaccess timeVSAvoidmemory capacity

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

The cache memory is segmented into multiple levels (L1, L2, L3) with different technologies. L1 uses SRAM for speed, L2 uses DRAM for capacity, and L3 uses NAND flash for high-density storage. This segmentation allows each level to optimize for its specific function, resolving the contradiction between speed and capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical cache architecture that adds temporal and spatial dimensions to memory organization. Data is cached across multiple levels with different access characteristics, allowing the system to achieve both fast access (through L1 SRAM) and large capacity (through L2/L3 DRAM and flash) simultaneously.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If DRAM is used for L2 cache to increase memory capacity, then memory density improves, but power consumption increases

Engineering Contradiction:

Improvememory densityVSAvoidpower consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The system dynamically manages the L2 cache by selectively powering down or reducing refresh operations for inactive DRAM regions. The controller monitors access patterns and adjusts power states accordingly, allowing the system to maintain high memory density while reducing power consumption during low-activity periods.

Inventive Principle:

Principle #15Dynamics

3Area of stationary object

If NAND flash is used for L2 cache to reduce die size, then area efficiency improves, but access speed decreases

Engineering Contradiction:

Improvedie sizeVSAvoidaccess speed

Core Design Contradiction:

Area of stationary objectVSSpeed

Solution Approach 1:

The cache is segmented into volatile (SRAM, DRAM) and non-volatile (NAND flash) portions. The volatile portions handle frequently accessed data requiring fast access, while the non-volatile portion stores less frequently accessed data, maximizing area efficiency without significantly impacting overall access speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system pre-loads data from NAND flash into DRAM or SRAM caches before it is needed for processing. This preliminary action ensures that when data is actually accessed, it is already in faster memory, masking the slower access speed of NAND flash.

Inventive Principle:

Principle #10Preliminary action

4Adaptability or versatility

If FTL is implemented to enable random access to NAND flash, then access flexibility improves, but operating life decreases

Engineering Contradiction:

Improveaccess flexibilityVSAvoidoperating life

Core Design Contradiction:

Adaptability or versatilityVSDuration of action of stationary object

Solution Approach 1:

The patent introduces an intermediary caching layer (DRAM and SRAM) between the host and NAND flash. This intermediary absorbs the wear from frequent access operations, allowing the FTL to manage flash wear more effectively by batching writes and reducing erase cycles, thereby extending operating life while maintaining access flexibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

5Quantity of substance

If host DRAM is allocated for SSD cache to reduce on-board DRAM requirements, then cost is reduced, but host performance may be adversely impacted

Engineering Contradiction:

Improveon-board DRAMVSAvoidhost performance

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The SSD controller autonomously manages the host memory buffer, independently allocating and managing cache space within the host DRAM. This self-service approach allows the SSD to optimize its caching strategy without interfering with host operations, as the controller can identify and manage cache regions that do not conflict with host workloads.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS9563382B2Methods, systems, and computer readable media for providing flexible host memory buffer

Publication Date: 2017.02.07 SANDISK TECHNOLOGIES LLC

AI summary

Methods, systems, and computer readable media for providing a flexible host memory buffer are disclosed. One method includes allocating an amount of host memory as a host memory buffer accessible by a solid state drive (SSD) as a cache for SSD data. The method further includes caching data from the solid state drive in the host memory buffer. The method further includes monitoring utilization of the host memory buffer. The method further includes dynamically increasing or decreasing the amount of host memory allocated for the host memory buffer based on the utilization.