Flexible Inter-Processor Communication Topology for Accelerator Latency
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Solution Overview
Problem
Current high-speed inter-processor communication systems face bottlenecks due to fixed interconnection topologies and the limitations of standard computing buses, which cannot keep pace with the data processing speed of accelerators, leading to increased latency and reduced performance in computing clusters.
Innovation Solution
A high-speed inter-processor communications architecture with a flexible interconnect topology using multiple daughter boards and interconnection ports, allowing for configurable and adaptable interconnections between accelerators, enabling mesh or fabric topologies and bypassing conventional data pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard computing buses (e.g., PCIe) are used for interconnection, then device compatibility and ease of manufacture are improved, but data transmission speed becomes insufficient and bottlenecks occur
Solution Approach 1:
The system segments the interconnection architecture into multiple high-speed pathways by introducing multiple interconnection ports (first, second, third ports) on each accelerator card, replacing the single bottlenecked PCIe bus with parallel high-speed communication channels
Solution Approach 2:
The patent transitions from a single-dimension PCIe bus architecture to a multi-dimensional interconnection topology where accelerators can communicate through multiple ports and paths, enabling mesh or fabric topologies that provide redundant and parallel data transmission routes
2Stability of the object's composition
If fixed interconnection topologies are used, then system stability and ease of manufacture are improved, but adaptability to different computational needs deteriorates
Solution Approach 1:
The system implements dynamic interconnection topology by allowing configurable routing between multiple interconnection ports, where the communication paths can be dynamically adjusted based on computational requirements while maintaining stable physical connections through standardized card slots and port interfaces
Solution Approach 2:
Each accelerator card is designed with multiple universal interconnection ports that can support various topologies (mesh, fabric, etc.) and different computational workloads, making the system universally adaptable to different applications while maintaining stable standardized interfaces
3Productivity
If multiple interconnection ports per accelerator are implemented, then data exchange speed and flexibility are improved, but device complexity increases
Solution Approach 1:
The system maintains homogeneity by implementing identical multiple interconnection ports on each accelerator card, allowing for uniform routing logic and simplified control software despite the increased physical connectivity, thereby managing complexity through standardization
Data Source
AI summary
A computing device has a motherboard, at least two daughter boards communicably connected to the motherboard, each of the at least two daughter boards having at least a specialized processor and a high-speed inter-processor communications port; and at least two high-speed inter-processor communication interconnects connecting at least two of the high-speed inter-processor communications ports. The configuration enables a flexible topology architecture, e.g., for different applications, and rapid reuse of system components even when new specialized processors become available.