Flexible Multi-Layer Interconnect Structure for Semiconductor Re-Spin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of modern semiconductor devices requires iterative re-spinning of metal layers, which is costly and time-consuming, especially when modifying lower-level metal layers, due to their complexity and the need to re-form all overlying layers.
Innovation Solution
A flexible interconnect structure using metal lines and vias across multiple layers allows for modifying electrical connections between nodes by forming or breaking conductive paths at any metal layer, reducing the number of layers that need to be re-spun and thus minimizing costs and scheduling issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If lower-level metal layers are modified, then circuit functionality can be changed, but the cost and complexity increase significantly due to needing to re-form all overlying layers
Solution Approach 1:
The patent segments the interconnect structure into multiple independent metal layers (first metal layer, second metal layer, third metal layer) that can be modified independently. Each layer contains conductive elements (metal lines, vias, contact holes) that can be selectively changed without affecting other layers, allowing circuit modifications without re-spinning the entire device.
Solution Approach 2:
The patent incorporates preliminary action by forming multiple metal layers with conductive elements during the initial fabrication process, creating a structure that enables future modifications. The interconnect structure is pre-configured with redundant conductive paths and elements that can be selectively activated or deactivated in later iterations without requiring complete re-fabrication.
2Reliability
If lower-level metal layers are re-spun, then design errors can be corrected, but the time and cost increase due to re-forming multiple overlying layers
Solution Approach 1:
The patent divides the interconnect structure into separable metal layers that can be independently modified. When design errors are detected, only the specific metal layer containing the error needs to be re-formed, while other layers remain intact. This segmentation dramatically reduces the time required for iterative design corrections compared to re-spinning the entire device.
Solution Approach 2:
The patent creates a dynamic fabrication process where the scope of re-spinning operations can be adjusted based on the location and nature of design errors. The multi-layer interconnect structure allows the process to adapt by targeting only the necessary layers for modification, making the re-spinning process flexible and efficient rather than requiring complete device re-fabrication.
3Ease of operation
If multiple metal layers are used for interconnects, then signal transmission between functional elements is enabled, but the cost of modifying lower layers increases proportionally to the number of overlying layers
Solution Approach 1:
The patent segments the interconnect system into multiple independent metal layers, each capable of being manufactured and modified separately. This segmentation allows signal transmission across layers while enabling cost-effective modifications by targeting only the specific layer that requires changes, rather than requiring re-manufacturing of all overlying layers.
Solution Approach 2:
The patent creates a universal interconnect architecture where multiple metal layers serve both signal transmission and modification purposes. The same multi-layer structure that enables complex signal routing also provides the flexibility for iterative design changes, making the manufacturing process adaptable to different design requirements without proportionally increasing costs.
Data Source
AI summary
Embodiments of present invention provide methods and apparatuses for connecting and/or disconnecting nodes in a semiconductor device. Embodiments of the apparatus may include a plurality of metal layers formed above a substrate and an interconnect structure formed between first and second nodes in the plurality of metal layers. The interconnect structure includes one or more metal lines formed in each of the metal layers. The metal lines are connected by a plurality of vias. Modifying one of the metal lines in any one of the metal layers changes an electrical connection between the first and second nodes.