Flexible Interposer Assembly for Low-Height Stacked Dies
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Solution Overview
Problem
Conventional semiconductor packages with stacked semiconductor dies require significant vertical separation for wire bonding, leading to increased package height, reduced top mold clearance, and susceptibility to damage due to wire damage or shorting, which complicates signal routing and limits component placement.
Innovation Solution
A flexible interposer with embedded conductive traces is used between semiconductor dies to provide electrical connections, eliminating the need for wire bonding and reducing the vertical separation, thereby decreasing the overall package height and enhancing protection against damage and shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used for electrical connections between stacked semiconductor dies, then electrical connectivity is achieved, but package height increases and susceptibility to wire damage increases
Solution Approach 1:
The patent extracts the wire bonding process entirely by embedding conductive traces directly within the semiconductor die structure. This eliminates the external wire bonds that protrude and are susceptible to damage, while maintaining electrical connectivity through integrated trace pathways that route signals internally without requiring additional vertical space.
Solution Approach 2:
The patent merges the electrical connection function with the semiconductor die structure itself by integrating conductive traces into the die layers. Instead of using separate wire bonds, the connection pathway is combined with the die substrate, eliminating the need for external wiring and reducing overall package height while improving reliability.
2Ease of manufacture
If significant vertical separation is provided for wire bonding, then wire bonding can be performed, but package height increases and top mold clearance is reduced
Solution Approach 1:
The patent removes the requirement for significant vertical separation by eliminating the wire bonding process. Conductive traces are embedded within the die structure at various layers, allowing electrical connections to be established without requiring the dies to be separated by large distances, thereby reducing package height while maintaining manufacturability.
Solution Approach 2:
The patent transitions from three-dimensional wire bonding (requiring vertical separation and external wiring) to a two-dimensional integrated trace system embedded within the die planes. This dimensional shift allows electrical connections to be made within the die structure itself, eliminating the need for additional vertical space and reducing package height.
3Reliability
If conventional spacers are used for separation, then vertical separation is achieved, but package height increases
Solution Approach 1:
The patent combines the separation function with the electrical connection function by integrating conductive traces within the die structure itself. The die layers are separated by bonding interfaces that provide both mechanical support and electrical connectivity, eliminating the need for additional spacer components that would increase package height while maintaining protection against shorting.
Solution Approach 2:
The patent extracts the spacer component entirely by using the bonding interfaces between die layers to provide both separation and structural support. The conductive traces are embedded within the die layers themselves, eliminating the need for external spacers while maintaining adequate separation and protection against electrical shorting.
Data Source
AI summary
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die in a stacked arrangement with the first semiconductor die, and a flexible interposer disposed between the first semiconductor die and the second semiconductor die. The flexible interposer may include a first flexible layer, a second flexible layer, and a conductive trace disposed between the first flexible layer and the second flexible layer. A spacer portion of the flexible interposer may space the first semiconductor die from the second semiconductor die. A connecting portion of the flexible interposer may extend from the spacer portion beyond edges of the first semiconductor die and the second semiconductor die.