Flexible Logic Unit Context Switching for Real-Time FPGA Tasks
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Solution Overview
Problem
Existing FPGA-based controllers in automotive ECUs face challenges with slow context switching, high resource occupation, and increased context switching delay due to the need for external data transfer and lack of fault tolerance, which are not adequately addressed by current solutions.
Innovation Solution
The invention provides a flexible logic unit (FLU) with data store and restore circuits for pre-loading and post-storing task data during execution, configuration bit storage circuits for fault-tolerant operation, and output circuits for safe task switching, enabling fast and safe time-sliced context switching without disturbing ongoing tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the FPGA size is made bigger to handle multiple tasks, then the task handling capability is improved, but the cost increases significantly
Solution Approach 1:
The patent divides the FPGA into multiple banks, each bank capable of independently executing tasks. This segmentation allows the FPGA to handle multiple tasks simultaneously without requiring a single large FPGA, thus reducing overall cost while maintaining task handling capability.
Solution Approach 2:
Each FPGA bank is designed to be universal and can execute any task by loading appropriate configuration data. This multi-functionality eliminates the need for dedicated hardware for each task, allowing one FPGA to replace multiple specialized FPGAs, thereby reducing total FPGA size and cost.
2Adaptability or versatility
If the FPGA content is re-loaded each time task switching is required, then task flexibility is improved, but the switching speed becomes too slow for real-time operating systems
Solution Approach 1:
The patent pre-loads configuration data for multiple tasks into configuration memory before task execution begins. When task switching is required, the pre-loaded configuration data is already available, eliminating the need for slow re-loading operations during critical task switching moments.
Solution Approach 2:
The patent introduces configuration memory as an intermediary between the task management system and the FPGA banks. This intermediary buffer stores configuration data ready for quick transfer to FPGA banks, enabling fast context switching without directly re-loading from external sources during task transitions.
3Reliability
If the FPGA stops activity during application loading, then data integrity is improved, but the productivity and real-time performance deteriorate
Solution Approach 1:
The patent enables continuous task execution across multiple FPGA banks while configuration data is being prepared and transferred. By maintaining active processing in other banks during configuration updates, the system avoids complete stops and maintains real-time productivity while ensuring data integrity through controlled configuration transitions.
4Reliability
If multiple independent ECUs are used to control power-train elements, then the reliability of control is improved, but the cost and system complexity increase
Solution Approach 1:
The patent combines multiple ECU functions into a single FPGA-based controller by dividing the FPGA into multiple banks, each capable of independent task execution. This merging reduces the total number of ECUs and system complexity while maintaining control reliability through the distributed bank architecture that can independently handle critical control functions.
Data Source
AI summary
The invention applies to the context of an electric machine system where the digital control is handled with a FPCU component. This applies to application domains like but not limited to the automotive domain. The invention enables fast and safe time sliced context switching for application tasks mapped in FLU e FPGA matrix, similar as for the task context switching in a microprocessor, with the goal to maximize the usage of all computation resources of the FLU over time.