Flexible Logic Unit Context Switching for Real-Time FPGA Tasks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FPGA-based controllers in automotive ECUs face challenges with context switching due to high resource occupation and increased context switching delay, especially when handling multiple tasks and requiring fault tolerance and low power consumption, as existing solutions are either too expensive or too slow for real-time operations.
Innovation Solution
The implementation of a fast and safe time-sliced context switching mechanism for application tasks mapped in FLU eFPGA matrices, which includes a data store and restore circuit and configuration bit storage circuit, allowing for efficient use of computation resources, low-cost integration of strong functional safety checks, and minimal clock cycles for data and configuration operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the FPGA size is made bigger to handle multiple tasks, then the processing capability is improved, but the cost becomes too expensive for production
Solution Approach 1:
The patent divides the FPGA into multiple tiles, each capable of independently executing a task. This segmentation allows the system to handle multiple tasks without requiring a single large FPGA, thus reducing cost while maintaining processing capability.
Solution Approach 2:
Each tile in the FPGA is designed to be universal and can be configured to execute different tasks. This multi-functionality allows a smaller FPGA with multiple tiles to replace a larger FPGA dedicated to a single task, reducing overall device complexity and cost.
2Adaptability or versatility
If the FPGA content is re-loaded each time task switching is required, then adaptability is improved, but the context switching delay becomes too slow for real-time operations
Solution Approach 1:
The patent pre-loads configuration data and task data into buffer memory before task switching is required. This preliminary action ensures that when a task switch is needed, the data is already available, eliminating delays and enabling real-time operation.
Solution Approach 2:
The patent introduces buffer memory as an intermediary between the task/data sources and the execution units. This intermediary pre-stores configuration and task data, allowing fast retrieval during task switching without requiring full FPGA re-loading, thus reducing context switching delay.
3Adaptability or versatility
If conventional context switching is implemented, then task switching is enabled, but the switching delay is not acceptable for real-time systems
Solution Approach 1:
The system pre-loads task data and configuration into buffer memory before switching is needed, so that context switching can occur almost instantly by simply pointing to the pre-loaded data, rather than loading it during the switch.
Solution Approach 2:
The patent creates copies of task data and configuration in buffer memory that can be quickly switched to without modifying the original sources. This copying mechanism enables fast context switching by simply changing which copy is active, rather than performing complex reconfiguration operations.
4Reliability
If multiple ECUs are used to control power-train elements, then reliability is improved, but cost increases due to the multiplicity of independent ECUs
Solution Approach 1:
The patent merges multiple ECU functions into a single FPGA-based controller. By dividing the FPGA into multiple independent tiles that can execute different tasks simultaneously, the system maintains the reliability benefits of multiple independent control units while reducing the overall number of physical ECUs and associated costs.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The invention applies to the context of an electric machine system where the digital control is handled with a FPCU component. This applies to application domains like but not limited to the automotive domain. The invention enables fast and safe time sliced context switching for application tasks mapped in FLU e FPGA matrix, similar as for the task context switching in a microprocessor, with the goal to maximize the usage of all computation resources of the FLU over time.