Flexible Multiplier for High-Precision Neural Processing
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Solution Overview
Problem
Existing neural processing units face challenges in performing high-precision calculations efficiently, often requiring more hardware resources and complexity when using high-precision multipliers.
Innovation Solution
A processing element and neural processing device that utilize a flexible multiplier capable of performing multiplication operations using both a first multiplier of low precision and a second multiplier of low precision, in response to a calculation mode signal, to achieve high-precision calculations with reduced hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-precision multipliers are used to perform high-precision calculations, then calculation precision is improved, but hardware complexity and resource requirements increase
Solution Approach 1:
The patent divides a high-precision multiplication operation into multiple low-precision multiplication operations. Specifically, it segments the multiplication into partial product groups that can be calculated using lower-precision multipliers, then combines these partial results through addition to achieve the final high-precision result. This segmentation allows the system to use simpler, lower-precision multiplier hardware while still achieving high-precision calculation outcomes.
Solution Approach 2:
The patent merges multiple low-precision multiplication results through addition operations to produce a high-precision result. By combining the partial product groups from multiple low-precision multipliers and using adders to sum these results, the system achieves high-precision calculation without requiring individual high-precision multiplier components.
2Measurement precision
If high-precision multipliers are used to perform high-precision calculations, then calculation precision is improved, but hardware resources increase
Solution Approach 1:
The patent segments the high-precision calculation task into multiple low-precision sub-tasks. By dividing the multiplication operation into partial product groups that can be handled by lower-precision multipliers, the system reduces the bit-width requirements of individual multiplier components, thereby reducing the overall hardware resource consumption while maintaining high-precision output through combination of results.
Solution Approach 2:
The patent uses multiple low-precision multipliers (cheaper, simpler components) instead of a single high-precision multiplier (expensive, complex component). Although multiple low-precision units are used, each individual unit consumes fewer hardware resources, and their combined output through addition achieves the desired high-precision result, effectively trading component quantity for component quality.
3Device complexity
If low-precision multipliers are used to reduce hardware complexity, then hardware complexity is reduced, but calculation precision deteriorates
Solution Approach 1:
The patent compensates for the limited precision of individual low-precision multipliers by merging multiple partial product results through addition operations. The aligner ensures proper alignment of partial products, and the adder combines them to produce a final result with higher precision than any individual low-precision multiplier could achieve alone, thus recovering and exceeding the original precision requirement.
Solution Approach 2:
The patent transitions from a single-dimension approach (one high-precision multiplier) to a multi-dimensional approach (multiple low-precision multipliers with additional alignment and addition stages). By adding the dimensions of partial product generation, alignment, and summation, the system achieves high-precision results through a expanded computational pathway that compensates for the lower precision of individual components.
Data Source
AI summary
The present disclosure discloses a processing element and a neural processing device including the processing element. The processing element includes a weight register configured to store a weight, an input activation register configured to store input activation, a flexible multiplier configured to generate result data by performing a multiplication operation of the weight and the input activation by using a first multiplier of a first precision or using both the first multiplier and a second multiplier of the first precision in response to a calculation mode signal and a saturating adder configured to generate a partial sum by using the result data.