Flexible NIC Host Interface for Multi-Protocol Compatibility

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Solution Overview

Problem

Existing network interface controllers (NICs) often lack support for various software interface languages, leading to compatibility issues based on vendor and model, which hinders efficient data transmission and processing in packet-switched networks.

Innovation Solution

Implementing a flexible host interface with a symmetric multi-processing (SMP) array in the hardware data path to support multiple protocols dynamically, allowing for adaptable driver integration and efficient network packet processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a traditional NIC interface is used, then the device complexity is reduced, but the adaptability to different software interface languages and protocols deteriorates

Engineering Contradiction:
Improveprotocol supportVSAvoidinterface complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The host interface is designed with a configurable protocol translator that can dynamically translate between multiple software interface languages (PCI, PCI-X, PCI Express, CXL) and protocols (PCI Configuration Space, Memory-Mapped I/O, Message-Signaled Interrupts). This universal design allows a single interface to perform multiple protocol functions, improving adaptability without requiring separate dedicated interfaces for each protocol type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The protocol translator is configured based on the specific NIC model and vendor requirements, allowing the interface to dynamically adapt its translation behavior. The system can adjust the translation mode and protocol handling characteristics to match the operational requirements of different NIC implementations, making the interface both adaptable and efficiently simple.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If a fixed protocol interface is implemented, then the device complexity is minimized, but the versatility across different NIC vendors and models deteriorates

Engineering Contradiction:
Improvevendor compatibilityVSAvoidinterface flexibility
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The protocol translator serves as an intermediary layer between the host processor and the NIC-specific interface requirements. It mediates the communication by translating standardized host interface signals into vendor-specific or model-specific protocol formats, enabling broad vendor compatibility while maintaining a simple, unified host interface design.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If multiple protocol translations are supported, then the adaptability improves, but the processing time increases

Engineering Contradiction:
Improveprotocol compatibilityVSAvoidtranslation latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The protocol translator is pre-configured with translation rules and mappings for multiple protocols during system initialization or firmware loading. By preparing the translation configurations in advance, the actual protocol translation during runtime requires minimal processing, reducing translation latency while maintaining support for multiple protocols.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12457276B2Technologies for managing a flexible host interface of a network interface controller
Publication Date: 2025.10.28 INTEL CORP
  • US12457276B2 patent drawing
  • US12457276B2 patent drawing
  • US12457276B2 patent drawing

AI summary

Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.