Flexible Pin Allocation for DDR SDRAM Controller Reuse
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Solution Overview
Problem
The reuse of DDR SDRAM controllers across different memory devices with varying pin configurations is impractical due to signal integrity issues and routing complexity, leading to inefficient and non-scalable board layouts.
Innovation Solution
A memory controller that generates an allocation table based on board layout information, programs registers, and uses multiplexers to ensure signal transmission from pads to corresponding pins without crossovers, allowing flexible pin allocation and reducing routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If physical connections are fixed between pins of memory and corresponding pads of controller to enable controller reuse, then controller adaptability improves, but routing complexity and board layer requirements increase due to crossovers and skew requirements
Solution Approach 1:
The patent implements dynamic pin allocation through a pin allocation register that can be programmed at reset time to match different board layouts. This allows the controller to adapt its pad-to-pin mapping dynamically rather than being fixed, enabling reuse across different memory configurations without increasing routing complexity.
Solution Approach 2:
The invention changes the parameter of pad-to-pin mapping by introducing a programmable pin allocation register. This register stores mapping information that can be modified based on the specific board layout and memory device configuration, allowing the same controller to work with different pin configurations without physical redesign.
2Adaptability or versatility
If a single controller is designed to work with multiple memory devices of different configurations, then device versatility improves, but signal integrity and skew requirements become harder to meet
Solution Approach 1:
The pin allocation register enables dynamic configuration of pad-to-pin mappings based on the specific memory device and board layout being used. This dynamic adaptation allows the controller to maintain signal integrity by optimizing the routing path for each specific configuration rather than using a fixed mapping that may not be optimal for all cases.
3Reliability
If controller physical design is tailored for each type of memory device, then signal integrity improves, but manufacturing efficiency and scalability deteriorate
Solution Approach 1:
The patent makes the controller universal by incorporating a pin allocation register that can be programmed to support different memory device configurations. This single controller design can serve multiple memory types and board layouts, eliminating the need to create custom controller designs for each memory device while maintaining signal integrity through proper programmable mapping.
Solution Approach 2:
The pin allocation register is programmed in advance at reset time with the appropriate pad-to-pin mapping information for the specific board layout and memory device. This preliminary configuration allows the controller to operate optimally for the specific application without requiring custom hardware design, improving manufacturing efficiency while maintaining signal integrity.
4Device complexity
If fixed board layouts are required for controller compatibility, then controller design simplicity improves, but placement optimization and routing flexibility are lost
Solution Approach 1:
The pin allocation register provides dynamic adaptability to different board layouts, allowing memory devices to be placed flexibly on the board without requiring fixed layouts. The controller can be programmed to match the actual board configuration, enabling placement optimization while keeping the controller design relatively simple.
Solution Approach 2:
The controller is designed to be universal and work with multiple board layouts through the programmable pin allocation register. This eliminates the requirement for fixed board layouts while maintaining controller design simplicity, as the same controller can adapt to different configurations through software programming rather than hardware redesign.
Data Source
AI summary
A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.