Flexible RAM Loading with Parallel Pin Switching for Faster Test

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Solution Overview

Problem

Current RAM loading methods for microcontroller devices involve serial data loading, which is time-consuming, especially when loading kilobits of data, leading to prolonged test operations and manufacturing bottlenecks.

Innovation Solution

A flexible RAM loading device and method that utilize a shift register and test register with multiplexers to enable parallel data loading from multiple pins, reducing the time required to load data into RAM by using available pins efficiently and switching between serial and parallel modes based on pin availability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If serial data loading is used for RAM loading, then device complexity is reduced, but loading time increases significantly

Engineering Contradiction:
ImproveRAM loading timeVSAvoidloading device complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The loading device dynamically switches between serial and parallel loading modes based on the number of available pins. When pins are available, the system configures multiplexers to enable parallel loading; when pins are constrained, it falls back to serial loading. This dynamic adaptability resolves the contradiction by optimizing loading speed without permanently increasing device complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The loading device is designed to perform multiple functions: it can operate in both serial loading mode (using minimal pins) and parallel loading mode (utilizing multiple pins when available). The shift register and multiplexer structure enable the same hardware to adapt to different pin availability scenarios, achieving universal functionality that resolves the time-complexity tradeoff.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If parallel data loading from multiple pins is implemented, then loading speed increases, but device complexity increases

Engineering Contradiction:
Improvedata loading speedVSAvoidloading device complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The loading device segments data input across multiple pins, each connected to separate multiplexer inputs. The shift register is divided into sections that can be independently configured. This segmentation enables parallel loading when pins are available while maintaining the option to use only a subset of segments when pins are constrained, thus improving productivity without permanently increasing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes operational parameters (number of active pins, multiplexer configuration, shift register mode) based on available resources. By dynamically adjusting these parameters, the device achieves high-speed parallel loading when conditions permit while maintaining simplicity when pins are limited, resolving the productivity-complexity contradiction.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If the loading device adapts to different pin availability, then versatility improves, but control complexity increases

Engineering Contradiction:
Improvepin configuration adaptabilityVSAvoidcontrol logic complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The loading device automatically detects the number of available pins and self-configures its operation mode without requiring complex external control logic. The system uses its own internal resources (pin count detection) to make configuration decisions, thereby improving versatility while minimizing the need for additional control complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4216222B1Methods and devices for flexible ram loading for test operation
Publication Date: 2024.06.19 STMICROELECTRONICS SRL
  • EP4216222B1 patent drawingFigure 1
  • EP4216222B1 patent drawingFigure 2
  • EP4216222B1 patent drawingFigure 3

AI summary

A flexible RAM loader including a shift register (302) that includes a first data section (302A) coupled with a serial data input, and a second data section (302B) selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register (304) comprising a selection bit to couple the second data section with the first parallel data input.