Flexible Register Access Bus for SOC IP Integration
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Solution Overview
Problem
System-on-a-chip (SOC) integrated circuits face limitations in hosting a large number of IP components due to physical space constraints and latency issues with conventional buses, which restricts functional capacity and timing closure.
Innovation Solution
A flexible register access bus (FRAB) architecture is introduced, allowing for efficient routing of access requests through interconnected request and completion cells, using identifiers and TAGs to facilitate communication between IP register modules, reducing latency and improving timing closure by enabling flexible extension of chain levels and cell numbers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional bus is used to connect IP components and their register modules, then the physical layout is simple, but the number of components that can be hosted is limited due to physical space constraints and timing closure difficulties
Solution Approach 1:
The bus architecture is segmented into multiple chain levels with distributed request cells and completion cells. Each cell can independently handle routing decisions, allowing the system to scale to many more IP components without overwhelming a single centralized bus controller. This segmentation enables the FRAB to host a greater number of IP components while maintaining manageable complexity at each node.
Solution Approach 2:
The patent introduces a multi-dimensional routing structure with chain levels and cell positions that add spatial organization to the bus architecture. Request packets contain chain level and cell position information that enables hierarchical routing through multiple dimensions, allowing efficient addressing and routing to numerous IP components distributed across the chip area without requiring a fully connected mesh.
2Area of stationary object
If a serial bus is used to connect a large number of IP components, then the physical space requirement is reduced, but significant latency is experienced which impairs SOC performance
Solution Approach 1:
The request path is divided into multiple hops through request cells, each capable of local routing decisions. This segmentation allows parallel processing of multiple requests through different chain levels and reduces contention at any single point, thereby reducing overall access latency while maintaining a compact physical footprint.
Solution Approach 2:
Request packets are pre-configured with routing information including chain level and cell position data before being injected into the FRAB. This preliminary action enables each request cell to make immediate routing decisions without waiting for complex arbitration, significantly reducing the time each request spends in transit across the chip.
3Adaptability or versatility
If the path between the bus and IP components is made long to accommodate more components, then more IP components can be connected, but timing closure becomes difficult to achieve
Solution Approach 1:
The physical path is segmented into standardized request cells with predictable propagation delays. Each cell contributes a known, bounded amount to the total path delay, making timing analysis and closure more predictable. This segmentation allows the system to extend to more IP components while maintaining reliable timing through controlled, modular delay accumulation.
Solution Approach 2:
The FRAB architecture dynamically adapts routing paths based on destination requirements. Request packets are routed through optimal combinations of chain levels and cells, allowing the system to find timing-friendly paths for long-distance connections while maintaining flexibility to accommodate varying component distributions and timing requirements.
Data Source
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AI summary
Some embodiments described herein provide a method for transmitting an access request via a flexible register access bus. An access request may be received to access resource on an integrated circuit. The access request may be translated to a request packet having a data format compliant with the flexible register access bus. A routing path may be determined for the request packet based on a target register associated with the request packet. The request packet may be transmitted via the routing path to the target register. Information within the request packet may be translated to a local access protocol for the target register. Access to the resource may then be obtained via the target register based on the local access protocol.