Flexible Register Timing Library for Circuit Optimization
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Solution Overview
Problem
Conventional static timing analysis in digital integrated circuits fails to effectively consider the correlation between propagation delay, setup time, and hold time, leading to suboptimal clock cycle determination and increased design iteration and area overheads.
Innovation Solution
A method utilizing a flexible register timing library that dynamically adjusts setup and hold slack to minimize the clock cycle by simulating various combinations of input signal conversion time, clock signal conversion time, and register load capacitance, reflecting the correlation among setup slack, hold slack, and actual propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional register timing library is used where propagation delay is considered unrelated to setup time and hold time, then the timing analysis is simpler, but the clock cycle cannot be minimized and extra design iteration time and circuit area overheads are required
Solution Approach 1:
The patent applies parameter changes by transitioning from a conventional timing library with fixed propagation delay values to a flexible timing library where propagation delay is dynamically adjusted based on setup slack and hold slack parameters. This allows the timing analysis to capture the actual correlation between these parameters, enabling clock cycle minimization without requiring additional design iterations or circuit area overheads.
Solution Approach 2:
The patent implements dynamics by making the propagation delay dynamic rather than static. In the flexible register timing library, the propagation delay changes according to the actual setup slack and hold slack values, allowing the timing analysis to adapt to different operating conditions and optimize the clock cycle accordingly.
2Measurement precision
If the propagation delay of the register is considered unrelated to setup time and hold time, then the register timing library is simpler, but the actual propagation delay correlation with setup slack and hold slack is not captured
Solution Approach 1:
The patent uses parameter changes to improve timing measurement accuracy by incorporating setup slack and hold slack as variable parameters that directly influence the propagation delay value. This creates a more accurate model of actual register behavior while managing library complexity through systematic organization of the flexible timing data.
Data Source
AI summary
Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library. First, registers are simulated respectively in a case of a plurality of groups of an input signal conversion time, a clock signal conversion time, and a register load capacitance, corresponding actual propagation delays at this time are obtained by changing setup slack and hold slack of the registers, and actual propagation delays of the registers under specific input signal conversion time, clock signal conversion time, register load capacitances, setup slack, and hold slack are obtained through linear interpolation, to establish a flexible register timing library; and then static timing analysis is performed on all register paths in a circuit by using the library, a minimum clock cycle under a condition of satisfying that a setup time margin and a hold time margin are both greater than zero is found by changing the setup slack and hold slack of the registers, thereby improving the performance of the circuit without changing the design of the circuit and without increasing the area overheads of the circuit.