Flexible Ripple Logic Cells for PLD Routing and Delay Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable logic devices (PLDs) face limitations in programmable logic block (PLB) utilization due to excessive routing resource consumption, which restricts the implementation of user designs and increases propagation delay.
Innovation Solution
The solution involves increasing the flexibility of PLBs and routing resources by exploiting symmetry within PLBs through input interchange and decomposing multiple input look-up tables (LUTs) into subcomponents, allowing interchangeable inputs, thereby reducing the burden on routing resources and enhancing the scope of functions that can be embedded in PLDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If routing resources are increased to improve PLB utilization, then PLB utilization is improved, but area consumption increases
Solution Approach 1:
The patent segments the routing resources into dedicated routing for carry signals and separate routing for sum/propagate signals. This segmentation allows independent optimization of routing paths, reducing overall routing resource consumption while maintaining PLB utilization efficiency.
Solution Approach 2:
The patent implements multi-functionality by allowing the same routing infrastructure to serve multiple purposes: carry chain routing, sum signal routing, and propagate signal routing. This universal routing approach reduces the total amount of routing resources needed compared to having separate dedicated routing for each signal type.
2Productivity
If routing resources are increased to improve PLB utilization, then PLB utilization is improved, but propagation delay increases
Solution Approach 1:
By segmenting carry routing from sum/propagate routing, the patent creates dedicated fast paths for carry signals that do not compete with other signals for routing resources. This reduces routing congestion and propagation delay while maintaining efficient PLB utilization.
Solution Approach 2:
The patent introduces carry select logic as an intermediary mechanism that resolves carry signals through optimized selection paths. This intermediary structure reduces the critical path delay by providing multiple routing options and selecting the fastest path, thereby reducing overall propagation delay while maintaining high PLB utilization.
3Productivity
If routing resources are increased to improve PLB utilization, then PLB utilization is improved, but power consumption increases
Solution Approach 1:
The patent segments power consumption by creating separate optimized routing paths for carry signals and sum/propagate signals. This segmentation allows for targeted power management where only the actively used routing paths consume power, reducing overall power consumption while maintaining high PLB utilization.
Solution Approach 2:
The patent applies local quality optimization by providing different routing characteristics for different signal types: fast dedicated routing for carry signals and standard routing for sum/propagate signals. This localized optimization reduces power consumption by avoiding the need for high-performance routing throughout the entire PLD, while still achieving high PLB utilization where needed.
Data Source
AI summary
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.