Flexible Semiconductor Device with Asymmetric Insulating Film Thickness
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Solution Overview
Problem
Conventional flexible semiconductor devices face challenges with parasitic capacitance across multilayered wiring and limited capacitor capacity due to the use of glass substrates, which hinder high-speed operation and flexibility.
Innovation Solution
A flexible semiconductor device design featuring an insulating film with a thicker first film thickness for the upper and lower wiring pattern layers compared to the gate electrode, minimizing parasitic capacitance and enhancing capacitor capacity, along with a sealing layer and specific metal and semiconductor material choices for improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a glass substrate is used to form the TFT element, then heat resistance and manufacturing stability are improved, but weight increases and flexibility is lost
Solution Approach 1:
The patent changes the substrate material parameter from glass to resin, fundamentally altering the thermal and mechanical properties. This allows the device to operate at lower temperatures suitable for resin while achieving the desired flexibility and weight reduction, even though heat resistance is compromised
Solution Approach 2:
The patent employs a resin substrate that can be processed at lower temperatures, accepting the limited thermal stability of the resin in exchange for significant gains in flexibility, weight reduction, and cost-effectiveness for large-area displays
2Speed
If the insulating film thickness is increased to reduce parasitic capacitance, then high-speed operation is improved, but capacitor capacity decreases
Solution Approach 1:
The patent applies different insulating film thicknesses to different functional regions: a first insulating film with thickness of 50-200 nm in the capacitor region to maintain capacity, and a second insulating film with thickness of 200-500 nm in the wiring region to reduce parasitic capacitance. This localized differentiation resolves the contradiction between speed and capacity
Solution Approach 2:
The insulating film structure is segmented into multiple layers with different thicknesses and materials tailored to specific functional requirements - the gate insulating film, first insulating film for capacitor, and second insulating film for wiring isolation, allowing optimization of each region's electrical characteristics
3Device complexity
If multilayered wiring is formed sequentially on the substrate, then device integration is improved, but parasitic capacitance increases
Solution Approach 1:
The patent uses a low-dielectric constant material (k=2.5-3.5) specifically for the second insulating film that isolates the multilayered wiring, locally reducing the parasitic capacitance effect in the wiring region while maintaining the necessary integration complexity
Solution Approach 2:
The patent employs composite insulating film structures combining different materials with different dielectric constants - the gate insulating film, first insulating film for capacitor, and second insulating film made of low-k material for wiring isolation - to simultaneously achieve high integration and low parasitic capacitance
Data Source
AI summary
A flexible semiconductor device includes an insulating film on which a semiconductor element is formed. The top and bottom surfaces of the insulating film have a top wiring pattern layer and a bottom wiring pattern layer, respectively. The semiconductor element includes a semiconductor layer formed on the top surface of the insulating film, a source electrode and a drain electrode formed on the top surface of the insulating film so as to contact the semiconductor layer, and a gate electrode formed on the bottom surface of the insulating film so as to be opposite the semiconductor layer. A first thickness, which is the thickness of the insulating film facing the source electrode, the drain electrode, the top wiring pattern layer, and the bottom wiring pattern layer, is greater than a second thickness, which is the thickness of the insulating film between the gate electrode and the semiconductor layer.