Flexible Sequencer Architecture for Solid State Memory Controller Parallelism
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Solution Overview
Problem
Current solid state memory controllers waste significant host time due to inefficient parallelism in accessing multiple flash memory devices, leading to prolonged wait periods during write and read operations.
Innovation Solution
A job/descriptor architecture is implemented to maximize parallelism by allowing each flash memory device to be operated independently, with a sequencer managing job queues and descriptors to utilize multiple devices in parallel, reducing the need for firmware intervention and optimizing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single channel is dedicated to one memory device, then the control simplicity is improved, but the parallelism and host time utilization are worsened
Solution Approach 1:
The patent segments the channel-memory device mapping by allowing multiple memory devices to share a single channel through descriptor-based control. Each memory device is assigned a descriptor that contains control information, enabling independent addressing and operation of multiple devices on the same channel, thus improving parallelism while maintaining manageable control through structured descriptor organization.
Solution Approach 2:
The descriptor acts as an intermediary between the controller and memory devices. It mediates the control signals by containing all necessary information (address, control commands, timing parameters) for a specific memory device operation, allowing the controller to manage multiple devices on a single channel without complex direct control logic for each device.
2Productivity
If firmware provides descriptors continuously to maximize parallelism, then the host time utilization is improved, but the complexity of coordinating multiple operations is worsened
Solution Approach 1:
The firmware prepares and provides multiple descriptors in advance before actual memory operations execute. By pre-programming the descriptors with all necessary control information and queuing them, the system can maximize parallelism without real-time coordination complexity. The descriptors are ready to be executed as soon as memory devices become available, eliminating the need for complex dynamic coordination.
Solution Approach 2:
The memory devices autonomously execute operations based on the descriptors provided by the controller. Each device independently processes its assigned descriptor without requiring continuous firmware intervention or complex coordination. The descriptor contains all necessary control information, allowing devices to self-manage their operations according to the pre-provided instructions.
Data Source
AI summary
A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks.