Flexible Substrate Internal Stacking Module for IC Package Height Reduction
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Solution Overview
Problem
Existing integrated circuit packaging technologies face challenges in reducing package dimensions, improving yields, and enhancing thermal dissipation while meeting high performance and environmental demands, particularly in multi-chip stacking configurations.
Innovation Solution
The integration of a flexible substrate with an internal stacking module, where a stacking module integrated circuit is coupled to the substrate and a flexible extension is bent over it, with a package body molded around both, facilitating efficient interconnects and reduced package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple integrated circuits are stacked in a multi-chip package to reduce board space, then board space is reduced, but package height increases and thermal dissipation deteriorates
Solution Approach 1:
The patent transitions from horizontal stacking (increasing height) to vertical integration within a planar footprint. The interposer substrate enables three-dimensional integration architecture where multiple ICs are connected through vias and conductive structures in the vertical dimension, allowing heat to dissipate laterally across a larger surface area rather than being confined to a compact vertical stack.
Solution Approach 2:
The interposer substrate acts as an intermediary between multiple ICs, providing a platform for lateral heat distribution. The interposer's extended surface area and thermal pathways enable heat to spread laterally across the substrate before dissipation, improving thermal management while maintaining a compact package footprint.
2Length of stationary object
If conventional package stacking methods are used to reduce package dimensions, then package height is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The interposer substrate is prepared in advance with pre-formed conductive pathways, vias, and connection structures before IC attachment. This preliminary preparation of the interposer enables subsequent IC mounting and wire bonding to proceed more efficiently, reducing overall manufacturing complexity despite the advanced packaging architecture.
Solution Approach 2:
The packaging system is segmented into distinct functional modules: the interposer substrate with its own conductive pathways, multiple ICs, and wire bond interconnects. This segmentation allows each component to be manufactured and tested independently using existing processes, then assembled into the final compact package, reducing overall manufacturing complexity.
3Productivity
If more integrated circuits are packed into a smaller physical space to meet consumer electronics demands, then device integration is improved, but thermal management becomes more difficult
Solution Approach 1:
The patent employs three-dimensional integration architecture where ICs are mounted on an interposer substrate with vertical vias and conductive pathways. This spatial reconfiguration allows heat to dissipate through multiple pathways including lateral conduction across the interposer and vertical pathways through the package structure, improving thermal management while maintaining high device integration.
Solution Approach 2:
The interposer substrate serves as a thermal intermediary, collecting heat from multiple ICs and distributing it across its extended surface area. The interposer's thermal pathways enable efficient heat spreading and dissipation, preventing localized thermal hotspots while maintaining high device integration density.
Data Source
AI summary
An integrated circuit package system includes: providing an integrated circuit substrate; forming an internal stacking module coupled to the integrated circuit substrate including: forming a flexible substrate, coupling a stacking module integrated circuit to the flexible substrate, and bending a flexible extension over the stacking module integrated circuit; and molding a package body on the integrated circuit substrate and the internal stacking module.