Flexible Switch Logic Programmable Pipeline Architecture
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Solution Overview
Problem
Network switch devices face increasing processing overhead and power consumption as network traffic grows, with existing solutions often requiring additional processors and memory that increase cost and real estate usage.
Innovation Solution
A flexible switch logic (FSL) subsystem with a multi-block architecture that processes resolution logic after multiple lookups, featuring a programmable pipeline architecture with six types of hardware blocks, allowing for flexible modification of switching decision behavior and reduced latency and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional processors and memory are added to handle increased network traffic demands, then processing capacity is improved, but device cost and real estate usage increase
Solution Approach 1:
The FSL subsystem implements a universal processing architecture that can handle multiple packet types and protocols using the same hardware resources. The programmable pipeline with six types of hardware blocks (parsers, match-action tables, flexible switch logic subsystems, special function blocks, editors, and bus multiplexers) can be dynamically configured to process different packet formats, eliminating the need for dedicated hardware for each protocol type.
Solution Approach 2:
The system employs dynamic packet processing where the pipeline configuration changes based on packet type. The parser identifies packet format and dynamically routes packets through appropriate processing stages. This dynamic adaptation allows the same hardware to efficiently handle varying traffic demands without requiring static over-provisioning for peak loads.
2Productivity
If additional processors and memory are added to handle increased network traffic demands, then processing capacity is improved, but device cost increases
Solution Approach 1:
The FSL subsystem serves as a universal processing engine that replaces multiple specialized processors. The programmable architecture with configurable pipeline stages can be programmed to handle different packet processing requirements, reducing the need for multiple dedicated hardware units and thereby lowering device cost while maintaining high processing capacity.
Solution Approach 2:
The system changes processing parameters dynamically based on packet characteristics. The parser extracts packet type information and configures the pipeline accordingly, allowing the same hardware to operate in different modes optimized for specific protocols. This parameter-based adaptation reduces hardware complexity compared to having separate fixed-function processors for each protocol.
3Ease of manufacture
If traditional fixed switching logic is used, then hardware implementation is simple, but adaptability to different packet types and protocols is limited
Solution Approach 1:
The FSL subsystem introduces dynamic reconfigurability to the switching logic. The pipeline architecture with programmable stages allows the hardware to adapt its behavior based on packet type. The parser identifies packet characteristics and dynamically configures processing parameters, enabling the same hardware structure to handle diverse packet formats and protocols efficiently.
Solution Approach 2:
The system implements self-service through automated packet analysis and pipeline configuration. The parser automatically identifies packet type and triggers appropriate processing modes without external intervention. This self-adapting mechanism maintains ease of manufacture while achieving high versatility, as the system automatically adjusts to different protocols without requiring manual reconfiguration or complex control logic.
Data Source
AI summary
Flexible switch logic packet processing includes receiving a first packet associated with a particular traffic flow, generating a switching decision behavior in a first cycle of the particular traffic flow by selecting one or more processing floors of a programmable pipeline based on a received profile signal indicating a type of processing required for the first packet, and performing packet processing on the first packet using the selected one or more processing floors of the programmable pipeline. In some aspects, an ingress packet processor is configured to generate a first switching decision behavior using the selected processing floors of a first programmable pipeline in the ingress packet processor. In other aspects, an egress packet processor is configured to perform a packet action on the passed first received packet based on a second switching decision behavior using the selected processing floors of a second programmable pipeline in the egress packet processor.