Flexible Tape Underfill for IC Packaging Density and Yield
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Solution Overview
Problem
Current integrated circuit packaging techniques face challenges such as increased manufacturing costs and decreased yield due to vertically stacked MCMs, local and global planarization inconsistencies, and mechanical damage during test handling, which hinder the achievement of higher chip densities and efficient packaging.
Innovation Solution
The use of a flexible tape that is substantially conformal to the device, contacting interconnects on a substrate, allowing for reduced interconnect height, finer pitch, and improved durability, enabling pre-testing and protection against mechanical damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked MCMs are used to increase chip density, then the effective density of chips is improved, but manufacturing cost increases and product yield decreases due to assembly before testing
Solution Approach 1:
The patent implements preliminary testing of individual chips before they are assembled into the vertically stacked MCM structure. This is achieved by providing test access structures that allow chips to be tested in a flat configuration prior to stacking, enabling defective chips to be identified and removed before final assembly, thereby improving product yield while maintaining high chip density
2Quantity of substance
If vertically stacked MCMs are used to increase chip density, then the effective density of chips is improved, but manufacturing cost increases due to extra assembly steps
Solution Approach 1:
The patent performs preliminary testing and validation of chips before final stacking assembly, which prevents costly rework and scrap later in the manufacturing process. The test access structures enable early detection of defects, reducing the need for expensive post-assembly repairs and improving overall manufacturing efficiency
Solution Approach 2:
The patent divides the manufacturing process into separate stages: chip preparation with test access, individual chip testing, and final stacking assembly. This segmentation allows for independent optimization of each stage and enables parallel processing, thereby reducing overall manufacturing cost while achieving high chip density
3Adaptability or versatility
If the bottom chip is made larger to accommodate bond pads in vertically stacked MCMs, then the chip can support multiple connections, but the number of chips per semiconductor wafer decreases and manufacturing cost increases
Solution Approach 1:
The patent transitions from a two-dimensional layout where bond pads consume valuable chip area to a three-dimensional structure with test access protruding from the chip surface. This vertical dimension allows bond pads to be accessed from the side or top without increasing the chip's footprint, enabling more chips to be fabricated per wafer while maintaining full connection capacity
4Quantity of substance
If package on package structure is used for vertical stacking, then packaging density is improved, but local and global planarization inconsistencies occur
Solution Approach 1:
The patent employs a flexible underfill material that can conform to the varying heights and contours of stacked packages. This underfill material flows into the spaces between packages and cures to provide mechanical support and electrical isolation, effectively compensating for planarization inconsistencies and enabling successful package on package assembly
5Length of stationary object
If the mold cap is kept thin to accommodate ball diameters in package on package structure, then the package size is reduced, but the selection of epoxy mold compounds is restricted and handling becomes difficult
Solution Approach 1:
The patent uses composite underfill materials that combine the benefits of flexibility and structural support. These materials can be used with thinner mold caps while still providing adequate protection and handling capability, expanding the range of available epoxy mold compounds and improving manufacturability
6Strength
If large solder balls are used in package on package structure to contact the bottom package, then the connection is more robust, but the package size must increase to clear the bottom mold cap dimensions
Solution Approach 1:
The patent utilizes vertical stacking to achieve robust connections without increasing the horizontal package footprint. By arranging solder balls and connection points in three-dimensional space rather than spreading them out in two dimensions, the design maintains strong connections while minimizing the overall package area
7Productivity
If conventional packaging structures are used, then the package can be assembled, but the structures are prone to mechanical damage during test handling which slows throughput
Solution Approach 1:
The patent incorporates protective underfill material and reinforced test access structures before the chips undergo testing and handling. This preliminary protection prevents mechanical damage during test handling operations, reducing rework and improving test throughput while maintaining structural integrity
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a device to the substrate; providing interconnects on the substrate; and forming a flexible tape substantially conformal to the device and contacting the interconnects.