Flexible Substrate TFT With Offset Regions
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Solution Overview
Problem
Thin film transistors (TFTs) formed on flexible substrates exhibit varying characteristics due to alignment errors caused by thermal expansion, leading to inconsistent leakage currents depending on the location of formation.
Innovation Solution
A method of manufacturing TFTs with uniform characteristics involves forming a poly silicon layer on a flexible substrate, creating a gate stack with offset regions between dual gate stacks, and injecting a conductive dopant to ensure consistent off-set regions, regardless of the alignment, thereby maintaining identical device characteristics across different locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If TFTs are formed on flexible substrates using conventional single gate stack structure, then manufacturing process is simple, but leakage current varies significantly depending on formation location due to alignment errors from thermal expansion
Solution Approach 1:
The gate structure is divided into a first gate electrode and a second gate electrode that are physically separated by a gap. This segmentation creates two distinct gate regions that can independently control the channel, ensuring that leakage current is suppressed at both gate-channel interfaces regardless of alignment variations during manufacturing.
Solution Approach 2:
The patent introduces offset regions with different doping concentrations at specific locations between the gate electrodes and channel. The first offset region has a doping concentration different from the channel, creating a localized property that prevents carrier accumulation and reduces leakage current at the gate-interface, addressing the location-dependent leakage issue.
2Manufacturing precision
If symmetrical offset regions are used in conventional TFTs, then leakage current is reduced at mask aligning reference position, but alignment errors from thermal expansion cause asymmetrical offset regions at non-reference positions leading to increased leakage
Solution Approach 1:
By dividing the gate into two separate electrodes with a gap between them, the patent eliminates the need for precise symmetrical alignment of offset regions. Each gate electrode can be independently positioned, and the offset regions between each gate and the channel can be independently controlled, making the device performance insensitive to thermal expansion-induced misalignment.
Solution Approach 2:
The patent intentionally designs asymmetrical offset regions with different doping concentrations on either side of the channel. This controlled asymmetry compensates for potential alignment variations and ensures that leakage current is suppressed effectively regardless of the TFT's position on the flexible substrate relative to the mask aligning reference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform leakage current and device characteristics for TFTs formed on both mask aligning reference and non-reference positions, reducing the impact of alignment errors and thermal expansion on TFT performance.
Implementation Method 1
injecting a conductive dopant to ensure consistent off-set regions
Data Source
AI summary
A thin film transistor (“TFT”) includes a poly silicon layer formed on a flexible substrate and including a source region, a drain region, and a channel region, and a gate stack formed on the channel region of the poly silicon layer, wherein the gate stack includes first and second gate stacks, and a region of the poly silicon layer between the first and second gate stacks is an off-set region. A method of manufacturing the TFT is also provided.