Flexible Timebase for Eye Diagrams Using Digital PLL
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Solution Overview
Problem
Existing methods for generating a timebase for EYE diagrams in serial data communications systems face challenges in achieving stability and flexibility, particularly at high data rates, due to the need for expensive analog-to-digital converters and high-frequency sampling clocks, while also requiring separate crystals for different data rates and being limited by loop bandwidth.
Innovation Solution
A flexible timebase is achieved by recovering a clock signal from the input serial digital signal, subdividing it to produce a sine wave reference, using equivalent time sampling with a free running oscillator, and generating an eye pattern with a digital phase-locked loop comprising a phase detector, loop filter, and numerical controlled oscillator, which allows for jitter demodulation analysis without requiring high-cost converters or complex analog designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PLL derived timebase is used to provide flexibility for multiple data rates, then adaptability is improved, but timebase stability deteriorates due to the variable nature of PLL
Solution Approach 1:
The timebase generation is segmented into two independent parts: a stable free-running crystal oscillator providing the base timebase, and a separate PLL circuit that only processes the timing information without affecting the core timebase stability. This allows the system to achieve both stability from the crystal and flexibility from the PLL.
Solution Approach 2:
A crystal oscillator serves as an intermediary between the stable timebase requirement and the flexible PLL requirement. The crystal provides a stable reference that the PLL can lock onto, allowing the system to derive both stable and flexible timebase characteristics from this intermediate component.
2Stability of the object's composition
If a phase-locked crystal is used for single data rate, then timebase stability is improved, but adaptability deteriorates requiring separate crystals for each standard
Solution Approach 1:
A single crystal oscillator is designed to work with multiple data rates by combining it with a programmable PLL circuit. The crystal provides universal stability across all standards while the PLL's adjustable loop bandwidth and division ratios enable support for multiple data rate standards without requiring separate crystals for each.
3Speed
If direct digital synthesis is used to overcome crystal bandwidth limits, then loop bandwidth is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog DDS circuits with a simpler digital approach using a programmable counter and digital logic. Instead of using analog voltage-controlled oscillators and complex RC networks, the system uses digital timebase generation with a counter that can be programmed to provide the required loop bandwidth without the complexity of analog design.
4Measurement precision
If equivalent time sampling with high bandwidth sampler is used, then measurement precision is improved, but device complexity and cost increase due to expensive ADCs and high frequency clocks
Solution Approach 1:
The system dynamically adjusts the sampling rate and timebase frequency based on the actual data rate being measured. Instead of requiring a fixed high bandwidth sampler and high frequency clock, the system can adapt its sampling parameters to match the incoming signal, reducing the requirements for expensive hardware components while maintaining measurement precision.
Data Source
AI summary
A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. The digital phase-locked loop feedback is subtracted from the linear ramp to provide the input to the loop filter.