Flexible Transistor Nanowire Doping and Printing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for fabricating transistors on flexible substrates using silicon nanowires face challenges such as limited channel length precision, high contact resistances, and increased channel resistance due to processing variations and temperature constraints, which affect transistor performance and flexibility.
Innovation Solution
A field-effect transistor design featuring semiconductor nanostructures with high and low doping concentration regions, where the high concentration regions are connected to the source and drain electrodes and the low concentration region overlaps with the gate electrode, allowing for precise channel length control and reduced contact resistances without requiring high-temperature processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor processing techniques (lithography, vacuum evaporation, etching) are used for transistor fabrication, then manufacturing precision and device performance are maintained, but production cost increases and equipment requirements become tremendous
Solution Approach 1:
The patent replaces conventional mechanical semiconductor processing techniques (lithography, vacuum evaporation, etching) with a printing-based fabrication method. This substitution uses printing technology to deposit semiconductor materials and form transistor structures, significantly reducing equipment requirements and production cost while maintaining manufacturing precision
Solution Approach 2:
The patent changes the fabrication process parameters from high-temperature vacuum processes to low-temperature printing processes. By using printing technology, the process temperature is reduced, enabling the use of flexible substrates while maintaining transistor fabrication precision
2Manufacturing precision
If high-temperature processes are used for silicon film formation, then single crystal quality is improved, but substrate material selection is restricted and flexible substrates cannot be used
Solution Approach 1:
The patent changes the process temperature parameter from high-temperature to low-temperature processing. By using printing technology, single crystal silicon films can be formed at low temperatures, enabling the use of flexible substrates while maintaining crystal quality
Solution Approach 2:
The patent uses pre-synthesized silicon nanowires with controlled crystal structures as printing material. The nanowires are prepared in advance with desired single crystal properties, allowing low-temperature deposition while maintaining crystal quality on flexible substrates
3Ease of manufacture
If silicon nanowires are used as semiconductor material in printing processes, then low cost and flexibility are achieved, but channel length precision is limited by processing variations
Solution Approach 1:
The patent pre-synthesizes silicon nanowires with controlled lengths and crystal structures before printing. By preparing the nanowires in advance with precise dimensional control, the channel length precision is improved while maintaining the advantages of printing processes
Solution Approach 2:
The patent uses silicon nanowires with locally optimized properties, including controlled doping concentrations and crystal orientations. The nanowires are engineered to have specific qualities in different regions, improving channel length precision while maintaining printing process feasibility
4Ease of manufacture
If conventional transistor structures are used with uniform doping, then manufacturing is simplified, but contact resistance is high and transistor performance is limited
Solution Approach 1:
The patent uses silicon nanowires with non-uniform doping concentrations, where high-doping regions are created at contact areas to reduce contact resistance. The doping concentration varies locally along the nanowire, optimizing both electrical performance and maintaining relatively simple manufacturing
Solution Approach 2:
The patent pre-dopes the silicon nanowires with varying concentration profiles before printing. The nanowires are prepared in advance with optimized doping distributions, including high-doping regions at contact points, which reduces contact resistance while maintaining manufacturing simplicity
Data Source
AI summary
A source electrode 105 which is connected to a portion of at least one semiconductor nanostructure103 among a plurality of semiconductor nanostructures, a drain electrode 106 connected to another portion of the semiconductor nanostructure 103, and a gate electrode 102 capable of controlling electrical conduction of the semiconductor nanostructure 103 are included. The semiconductor nanostructures 103 include a low concentration region 108 having a relatively low doping concentration and a pair of high concentration regions 107 having a higher doping concentration than that of the low concentration region 108 and being connected to both ends of the low concentration region 108. The doping concentration of the high concentration regions 107 is 1×1019 cm−3 or more; the length of the low concentration region 108 is shorter than a length of the gate electrode 102 along a direction from the source electrode 105 to the drain electrode 106; and the length of the gate electrode 102 is shorter than the interspace between the source electrode 105 and the drain electrode 106.