Flexible Vector Floating Point Unit with Crossbar Routing
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Solution Overview
Problem
Current microprocessors and digital signal processor chips face limitations in floating point operation performance due to insufficient support for a wide variety of operation types and slowed vector operations caused by required data permutations.
Innovation Solution
A flexible vector arithmetic unit with multiple interconnected floating point multipliers and adders, capable of performing SIMD, FFT Butterfly, affine, and dual linear interpolation operations, along with the use of mini-float formats to conserve memory and extend dynamic range, is introduced.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional micro-architectures with separate integer and floating point units are used, then the device complexity is manageable, but the floating point operation performance is limited and cannot support a wide variety of operation types
Solution Approach 1:
The patent implements a universal arithmetic unit that can perform multiple floating point operations (addition, subtraction, multiplication, division, square root, reciprocal, reciprocal square root) using a common hardware structure. The unit uses configurable operand routing and a single operational code input to select different operations, eliminating the need for separate dedicated units for each operation type while maintaining high performance.
Solution Approach 2:
The arithmetic unit employs dynamic operand routing where the source and destination of data flow are configurable based on the operation being performed. The unit can dynamically select which operands to use as inputs and how to route them through the computational logic, allowing the same hardware to adapt to different operation types without requiring static dedicated paths for each operation.
2Reliability
If data permutations are performed before or after floating point operations, then the correctness of vector operations is ensured, but the vector operation speed is necessarily slowed down
Solution Approach 1:
The patent performs data permutation and reordering operations as part of the operand preparation stage, before the actual floating point computation begins. By pre-organizing the data in the correct format and order, the unit eliminates the need for post-computation permutation, allowing the computational units to work continuously without idle cycles waiting for data reordering.
Solution Approach 2:
The patent combines the data permutation logic with the operand routing mechanism of the arithmetic unit. The same configurable switching fabric that routes operands to the computational units also performs the necessary reordering and permutation, merging two functions into a single integrated system rather than requiring separate permutation stages before and after computation.
3Measurement precision
If full precision floating point formats are used, then the calculation accuracy is maintained, but the memory usage increases and dynamic range is limited
Solution Approach 1:
The patent applies different precision formats to different parts of the computation based on local requirements. Critical intermediate results that require high precision for accurate final results are maintained in full precision, while less critical values can use reduced precision formats. This allows the system to optimize memory usage by applying precision only where locally required rather than uniformly across all data.
Solution Approach 2:
The arithmetic unit supports configurable precision parameters that can be adjusted based on the specific computation being performed. The unit can operate in different precision modes (full precision, reduced precision, integer modes) and can dynamically change the parameter settings to match the requirements of different algorithms, balancing accuracy requirements against memory constraints.
Data Source
AI summary
Arithmetic units and methods for floating point processing are provided. In exemplary embodiments, data paths to and from multiple multipliers and adders are flexibly combined through crossbars and alignment units to allow a wide range of mathematical operations, including affine and SIMD operations. The micro-architecture for a high-performance flexible vector floating point arithmetic unit is provided, which can perform a single-cycle throughput complex multiply-and-accumulate operation, as well as a Fast Fourier Transform (radix-2 decimation-in-time) Butterfly operation.