Hierarchical Prototyping for Electronic Design Timing Analysis
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Solution Overview
Problem
Conventional top-down timing budget analysis for electronic circuit designs is time-consuming and inefficient, often failing to identify timing errors early in the design cycle due to excessive computing resources and unrealistic budgeting, leading to potential product failures.
Innovation Solution
Implementing flexible abstraction models (flexmodels) that replace internal circuit paths with smaller models using flexible filler cells, optimizing interface paths to ensure accurate timing and physical characteristics, allowing for early-stage identification of timing issues and efficient analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional top-down timing budget analysis is used, then timing analysis can be performed on the circuit design, but the process takes an excessive amount of time and computing resources
Solution Approach 1:
The patent divides the circuit design into hierarchical levels (top-level, block-level, and module-level), allowing timing analysis to be performed on segmented portions rather than the entire design at once. This segmentation enables early-stage analysis to focus only on critical portions of the circuit, significantly reducing analysis time while maintaining timing analysis accuracy.
Solution Approach 2:
The patent creates simplified prototype models that replicate the essential timing characteristics of the full circuit design. These prototypes contain only the critical paths and components necessary for timing analysis, allowing engineers to perform timely analysis on a representative subset rather than analyzing every component of the complete design.
2Reliability
If conventional top-down timing budget analysis is used, then timing analysis can be performed, but it fails to identify timing errors early in the design cycle due to unrealistic budgeting
Solution Approach 1:
The patent performs timing analysis at multiple hierarchical levels during the early design stages, before detailed implementation is complete. By analyzing timing at the top-level and block-level prototypes early in the design cycle, timing errors can be identified and corrected before they propagate through the full design, improving timing error detection capability.
Solution Approach 2:
The patent implements a feedback mechanism where timing analysis results from prototype models are used to refine and update the timing budget allocations. This feedback loop allows unrealistic budgeting assumptions to be identified and corrected, improving the accuracy of timing error detection in subsequent analysis iterations.
3Measurement precision
If detailed circuit implementation is performed before analysis, then complete timing analysis can be conducted, but the design cycle is extended and problems are discovered later
Solution Approach 1:
The patent enables timing analysis to be performed on segmented hierarchical levels without requiring complete detailed implementation of the entire circuit. Engineers can conduct meaningful timing analysis at the top-level and block-level prototypes, identifying critical timing issues early without waiting for full detailed design completion, thus improving design cycle efficiency.
Solution Approach 2:
The patent performs timing analysis on partial implementations and prototype models rather than requiring complete detailed design. By analyzing a representative subset of the circuit that captures critical timing paths, sufficient timing analysis completeness is achieved early in the design cycle, avoiding delays associated with waiting for full implementation.
Data Source
AI summary
Disclosed are improved methods, systems, and computer program products for implementing flexible models to perform efficient prototyping of electronic designs, which allows for very efficient analysis of the electronic designs. The flexible models allow many of the existing tools for designing electronics to perform more efficiently.