FlexRay Interface Partitioning for Synchronization

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Solution Overview

Problem

Synchronizing information transmissions between components in a FlexRay system is challenging due to differing clock domains and timing-criticality of data, leading to increased circuit size and power consumption in existing designs.

Innovation Solution

The interface between the controller host interface and protocol engine is partitioned using sorters to group information by timing and synchronization requirements, minimizing the number of hardware synchronizers and allowing for reduced area and power consumption, while maintaining flexibility to support different clock systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single bus is used for communication between controller host interface and protocol engine, then device complexity is reduced, but synchronization reliability deteriorates due to differing clock domains and timing-criticality of data

Engineering Contradiction:
Improveinterface structureVSAvoidsynchronization
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The interface is divided into multiple independent buses (first bus for static configuration data, second bus for dynamic data) with separate synchronizers for each bus. This segmentation allows each bus to be optimized for its specific timing requirements while maintaining overall system reliability, resolving the contradiction between simplicity and synchronization reliability.

Inventive Principle:
Principle #1Segmentation

2Reliability

If multiple synchronizers are used to handle different timing-criticality data, then synchronization reliability is improved, but device complexity and power consumption increase

Engineering Contradiction:
ImprovesynchronizationVSAvoidnumber of synchronizers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Different synchronizers are applied to different buses based on their specific timing requirements. The first bus uses a synchronizer optimized for static configuration data, while the second bus uses a synchronizer optimized for dynamic data with different timing-criticality. This local quality approach improves synchronization reliability for each data type while avoiding the need for a single overly complex synchronizer system.

Inventive Principle:
Principle #3Local quality

3Reliability

If dedicated buses are created for different data types, then synchronization performance is improved, but device complexity increases

Engineering Contradiction:
Improvesynchronization performanceVSAvoidinterface structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The controller host interface and protocol engine are designed to work with multiple bus types through universal interfaces. The same interface structure can accommodate both the first bus for static configuration data and the second bus for dynamic data, making the system multi-functional while maintaining good synchronization performance for each data type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7958281B2Method and apparatus for transmitting data in a flexray node
Publication Date: 2011.06.07 NXP USA INC
  • US7958281B2 patent drawing
  • US7958281B2 patent drawing
  • US7958281B2 patent drawing

AI summary

A method of transmitting data to a recipient comprising the steps of dividing the data into a plurality of groups, providing a synchronizing means for each of the groups, using the synchronizing means to synchronize the data in each group, and transmitting the data to a recipient characterized in that the data is divided in accordance with its synchronization requirements with the recipient.