FlexRay Bit Sampling Correction for Clock Jitter and Distortion

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Solution Overview

Problem

The existing FlexRay communication protocol is not robust enough to handle interferences such as clock jitter, clock frequency inaccuracy, noise, and signal distortion, limiting its ability to support all intended topologies due to its reliance on fixed strobe points and majority voting for error correction.

Innovation Solution

A system and method for signal error determination and correction that involves filterless sampling at 80 MHz, calculating error correction values frame-by-frame by measuring distortion in signal start segments, and applying corrections to individual bits using error correction values, while predicting logic states for improved robustness against signal distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If majority voting operation is used on bit samples, then error correction capability is improved, but robustness against clock jitter and signal distortion deteriorates

Engineering Contradiction:
Improveerror correction capabilityVSAvoidrobustness against clock jitter and signal distortion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by measuring the actual bit duration and strobe timing offset before performing bit sampling. The system calculates a compensation value based on the measured strobe timing offset and adjusts the sampling timing accordingly, preventing errors caused by clock jitter and frequency inaccuracies before they affect the sampling process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements parameter changes by dynamically adjusting the sampling timing based on measured parameters. The system measures the actual bit duration and strobe timing offset, then modifies the sampling instant by adding a compensation value derived from these measurements, adapting to varying signal conditions rather than using fixed sampling parameters.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If fixed strobe point is used for each cycle, then sampling simplicity is improved, but adaptability to signal distortion and clock frequency inaccuracy deteriorates

Engineering Contradiction:
Improvesampling simplicityVSAvoidadaptability to signal distortion and clock frequency inaccuracy
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The system performs preliminary measurement of the strobe timing offset and bit duration before sampling. By measuring these parameters in advance and calculating compensation values, the system prepares the necessary correction data before the actual bit sampling occurs, enabling adaptive sampling without complicating the core sampling operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by measuring the actual signal characteristics (bit duration, strobe timing offset) and using these measurements to adjust subsequent sampling operations. The system continuously monitors signal quality and adapts sampling timing based on measured deviations, creating a closed-loop system that maintains accuracy despite variations in clock frequency and signal distortion.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If sampling rate is increased to 80 MHz, then measurement precision of bit logic state is improved, but sensitivity to signal distortion and clock jitter deteriorates

Engineering Contradiction:
Improvebit logic state determination accuracyVSAvoidsensitivity to signal distortion and clock jitter
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The system measures the actual bit duration and strobe timing offset before performing high-rate sampling. By determining the precise timing characteristics in advance and calculating compensation values, the system prepares correction data that accounts for clock jitter and signal distortion before the 80 MHz sampling occurs, enabling accurate bit logic state determination despite high sensitivity to distortions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting the sampling instant based on measured signal characteristics. The system modifies the sampling timing parameter by adding a compensation value derived from measured bit duration and strobe offset, adapting the sampling process to actual signal conditions while maintaining the high 80 MHz sampling rate for precise bit logic state determination.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20090193317A1Method and system for signal error determination and correction in a flexray communication system
Publication Date: 2009.07.30 VELOCITY COMMUNICATION TECHNOLOGIES LLC
  • US20090193317A1 patent drawing
  • US20090193317A1 patent drawing

AI summary

A signal error determination and correction system is provided which comprises an error correction value calculation means which processes a predetermined segment of a signal to calculate an error correction value, and a signal correction means and prediction which applies the error correction value to at least part of the signal to correct the part of the signal. The invention further provides a method of signal error determination and correction.