FLI Interconnect Structure With Silicon Nitride Adhesion Layer

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Solution Overview

Problem

Existing first layer interconnect (FLI) production processes in semiconductor packaging face challenges such as adhesion, plating, and uniformity issues due to high temperatures and dual lithography methods, leading to misalignment, delamination, and oxidation risks, which compromise the integrity and reliability of surface finishes.

Innovation Solution

A single lithography method using an embedded silicon nitride film as a dry adhesion promoter layer, applied before the surface finish, to improve adhesion and reduce delamination risks, allowing for more reliable and cost-effective FLI production with better alignment and surface finish quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dual lithography methods are used for FLI production, then surface finish can be applied, but misalignment and delamination occur

Engineering Contradiction:
Improvesurface finish integrityVSAvoidalignment accuracy
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts the adhesion promoter function from the lithography process by using an embedded silicon nitride film that serves as a permanent adhesion layer, eliminating the need for the second lithography step and its associated alignment problems while maintaining surface finish integrity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The silicon nitride adhesion promoter layer is deposited in advance before the surface finish application, creating a stable foundation that prevents delamination without requiring subsequent lithography alignment steps

Inventive Principle:
Principle #10Preliminary action

2Reliability

If dual lithography methods are used for FLI production, then surface finish can be applied, but oxidation risks increase

Engineering Contradiction:
Improvesurface finish integrityVSAvoidoxidation risk
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The embedded silicon nitride film creates a protective environment for the copper interconnect, preventing oxidation by acting as a barrier between the copper and atmospheric oxygen, especially important during high-temperature soldering processes

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

3Productivity

If high temperatures are used during FLI production, then soldering can be performed, but surface finish materials diffuse into solder

Engineering Contradiction:
Improvesoldering processVSAvoidsurface finish uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The silicon nitride adhesion promoter layer acts as an intermediary barrier between the surface finish materials and the solder, preventing diffusion of surface finish materials into the solder during high-temperature reflow processes while maintaining good solderability

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The single lithography method enhances the reliability and integrity of FLI production by avoiding misalignment and delamination, ensuring a smoother surface finish and better connector contact, while reducing the risk of oxidation and operational costs.

Implementation Method 1

an embedded silicon nitride film as a dry adhesion promoter layer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

to protect them from oxidation

Methodology Applied
Scientific EffectOxidation resistance: Oxidation

Data Source

PatentUS20230420346A1Single lithography methods for interconnect architectures
Publication Date: 2023.12.28 INTEL CORP
  • US20230420346A1 patent drawing
  • US20230420346A1 patent drawing
  • US20230420346A1 patent drawing

AI summary

Various embodiments disclosed relate to a semiconductor assembly interconnect structure. The present disclosure includes an interconnect structure that case include a substrate, a metallic layer thereon, an adhesion promoter film formed over the metallic layer and forming a flat region over a flat portion of the metallic layer, a solder resist layer formed over the adhesion promoter film, an opening in the solder resist layer and the adhesion promoter film in the flat region of the adhesion promotion film, the opening connecting to the flat portion of the metallic layer, and a stacked electrical connector formed on the metallic layer within the opening. Methods of making an interconnect structure can include patterning a metallic layer on a substrate, depositing an adhesion promoter layer on the metallic layer opposite the substrate, patterning the adhesion promoter layer to expose selected portions of the metallic layer, and depositing a surface finish layer on the exposed selected portions of the metallic layer.