Flight Control Computer Synchronization Under Unknown Time Delay
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Solution Overview
Problem
Modern aircraft flight control systems face challenges in synchronizing dissimilar flight control computers used for control and monitoring modes, which is crucial for robust automatic piloting laws, especially when one computer has an unknown time advance or delay relative to the other.
Innovation Solution
A method and system for synchronizing two computers that compute control orders for aircraft control surfaces, involving iterative steps of computing, exchanging, determining signal pairs, product pairs, and remainder pairs to establish synchronized signals, even when one computer has a time advance or delay relative to the other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dissimilar redundant computers are used in flight control systems with COM/MON pairs, then system robustness against faults is improved, but synchronization difficulty increases due to unknown time advances or delays
Solution Approach 1:
The patent introduces an intermediary synchronization mechanism that uses exchanged bits and signal pairs as mediators between computers. Each computer computes bits based on control order changes, exchanges these bits with its partner, and uses the exchanged information to determine synchronized signals. This intermediary approach allows synchronization without requiring direct knowledge of time advances or delays between dissimilar computers.
Solution Approach 2:
The patent applies preliminary action by having computers pre-compute bits based on control order changes before exchange. The bits represent predetermined information about control order transitions, allowing the synchronization mechanism to work with prepared data rather than requiring real-time alignment. This preliminary computation simplifies the synchronization process despite unknown time differences.
2Measurement precision
If iterative synchronization steps are implemented to handle unknown time differences, then synchronization accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent segments the synchronization process into distinct iterative steps: computing bits based on control order changes, exchanging bits between computers, determining signal pairs from exchanged bits, computing product pairs, computing remainder pairs, and determining final synchronized signals. This segmentation allows each step to be handled independently with simple logic, reducing overall computational complexity while achieving accurate synchronization through multiple passes.
Solution Approach 2:
The patent uses partial action by computing only the necessary bits related to control order changes rather than exchanging complete control order data. The bit computation focuses on specific transitions (whether control orders differ from previous iterations), providing sufficient information for synchronization without the overhead of full data exchange. This partial approach reduces computational load while maintaining synchronization accuracy.
3Reliability
If bits are exchanged iteratively to determine synchronized signals, then reliability of control orders is improved, but communication overhead increases
Solution Approach 1:
The patent extracts only the essential synchronization information from control orders by computing single bits that represent whether control orders have changed. Instead of exchanging complete control order data or detailed timing information, the system extracts minimal bit representations that capture the necessary synchronization state. This extraction dramatically reduces communication overhead while maintaining the ability to achieve reliable synchronized control orders.
Data Source
AI summary
A method and system for synchronizing computers includes a bit computing module for computing of a bit by each computer, an exchange module, a bit signal pair determination module for determining a bit signal pair including the computed bit, a bit product pair determination module for determining a bit product pair indicating which bit equal to 1 of the bit signal pair of a computer can be combined with the bit of the bit signal pair determined for the other computer in the iteration n−1, a bit remainder pair determination module for determining a bit remainder pair indicating which bit equal to 1 of the bit signal pair of a computer in the iteration n is different from the bit of the bit signal pair of the other computer in the iteration n−1, a synchronized signal determination module for determining a synchronized signal based on the bit product pair and on the bit remainder pair.