Flight Control Computer Synchronization for Unknown Timing Offsets
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Solution Overview
Problem
Current aircraft flight control systems face challenges in synchronizing dissimilar flight control computers used for control surface actuators, which is crucial for robust implementation of autopilot laws, especially when one computer has an unknown temporal advance or delay relative to the other.
Innovation Solution
A method and system for synchronizing two computers that calculate control commands for aircraft control surface actuators, involving iterative steps of calculation, bit exchange, signal pair determination, product pair calculation, and synchronized signal determination to align control orders despite temporal offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dissimilar redundant computers are used in flight control systems, then system robustness against failures is improved, but synchronization between computers becomes difficult due to unknown temporal offsets
Solution Approach 1:
The patent introduces an intermediary synchronization mechanism that mediates between dissimilar computers with unknown temporal offsets. The method uses intermediate synchronization signals and iterative bit comparison to bridge the timing gap, allowing computers to reach agreement on control orders without requiring precise knowledge of each other's clock rates or initial offsets.
Solution Approach 2:
The patent applies preliminary action by performing iterative synchronization steps before final control order execution. The computers iteratively exchange bits, determine signal pairs, product pairs, and remainder pairs, and adjust their synchronization state in advance of actual control surface actuation, ensuring they are synchronized before critical operations.
2Adaptability or versatility
If computers with different clock rates are used, then hardware flexibility is improved, but precise synchronization becomes impossible using traditional methods
Solution Approach 1:
The patent applies dynamics by making the synchronization process adaptive rather than static. The iterative method dynamically adjusts to different clock rates by continuously exchanging synchronization information and adjusting the synchronization state based on received bits, allowing the system to accommodate varying hardware characteristics without sacrificing precision.
Solution Approach 2:
The patent uses feedback mechanisms where computers continuously exchange synchronization bits and adjust their state based on the received information. The iterative process incorporates feedback from previous synchronization attempts, using product pairs and remainder pairs to determine whether synchronization has been achieved and to guide further adjustment if needed.
3Measurement precision
If iterative synchronization steps are implemented, then synchronization accuracy is improved, but processing time and computational load increase
Solution Approach 1:
The patent applies partial action by implementing iterative synchronization steps only when needed to achieve the required level of synchronization accuracy. The method can terminate early if synchronization is achieved quickly, or continue with additional iterations if more precision is required, avoiding unnecessary computational overhead when full iteration is not needed.
Data Source
Figure 1~2
Figure 3A~3B
Figure 4~5
AI summary
- Method and system for synchronizing computers. - The synchronization system for computers (A) and (B) includes a calculation module (2) of bits per computer (A) and (B), an exchange module (3) of the calculated bit, a signal pair determination module (4) of bits including the calculated bit, a product pair determination module (5) of bits indicating which bit equal to 1 of the signal pair of bits of one computer (A, B) is combinable with the bit of the signal pair of bits determined for the other computer (A, B) at iteration n-1, a remainder pair determination module (6) of bits indicating which bit equal to 1 of the signal pair of bits of one computer (A, B) at iteration n is different from the bit of the signal pair of bits of the other computer (A, B) at iteration n-1, a synchronized signal determination module (7) from the product pair of bits and the remainder pair of bits.The system (1) therefore allows the signals produced by the computers (A, B) to be synchronized.