Flip Chip Backside Conductive Layer for Latchup Resistance
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Solution Overview
Problem
Integrated circuits, particularly those in flip chip configurations, are prone to latchup due to high energy ionized particles, which increases substrate resistance and costs when attempting to reduce it during manufacturing, making them more susceptible to latchup compared to wire bonded circuits.
Innovation Solution
A semiconductor device with an electrically conductive conformal layer is applied on the back surface of the integrated circuit, extending over the underfill material and substrate lead, providing a low resistance shunt across the substrate to reduce latchup occurrences, using a vapor phase transport process or sputter process to form the conformal layer independently of the integrated circuit fabrication facility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to reduce substrate resistance, then latchup resistance is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent transitions from wire bonding (three-dimensional connection) to a planar conformal layer deposited on the back surface of the substrate. This dimensional change simplifies the structure by eliminating the need for physical wire connections and bonding pads, reducing device complexity while maintaining low substrate resistance for latchup prevention
Solution Approach 2:
The patent replaces the mechanical wire bonding process with a vapor phase transport deposition process. Instead of physically attaching wires to bonding pads, a conformal conductive layer is deposited directly on the substrate back surface, eliminating mechanical bonding complexity while achieving the same electrical function of reducing substrate resistance
2Reliability
If substrate resistance is reduced during fab manufacturing, then latchup resistance is improved, but manufacturing process compatibility is worsened and costs increase
Solution Approach 1:
The conformal layer is deposited on the substrate back surface before the substrate is mounted in the final package. This preliminary action allows the low-resistance path to be established early in the manufacturing process, compatible with standard fab processes, without requiring additional steps after substrate mounting
Solution Approach 2:
The patent changes the physical state and deposition parameters by using vapor phase transport to deposit a conformal layer with controlled thickness and conductivity. This allows optimization of the layer's electrical properties (resistivity, thickness) to achieve the desired substrate resistance reduction while maintaining compatibility with existing manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The electrically conductive conformal layer effectively reduces latchup incidents by providing a low resistance path, improving the reliability and reducing manufacturing costs by integrating with existing digital integrated circuit processes without increasing costs.
Implementation Method 1
The electrically conductive conformal layer is formed by a vapor phase transport process of electrically conductive material through the aperture of the shadow mask onto the back surface of the substrate
Implementation Method 2
using a vapor phase transport process or sputter process to form the conformal layer
Data Source
AI summary
An integrated circuit is attached to a chip carrier in a flip chip configuration. An electrically conductive conformal layer is disposed on a back surface of the substrate of the integrated circuit. The electrically conductive conformal layer contacts the semiconductor material in the substrate and extending onto, and contacting, a substrate lead of the chip carrier. The substrate lead of the chip carrier is electrically coupled to a substrate bond pad of the integrated circuit. The substrate bond pad is electrically coupled through an interconnect region of the integrated circuit to the substrate of the integrated circuit. A component is attached to the chip carrier and covered with an electrically insulating material. The electrically conductive conformal layer also extends at least partially over the electrically insulating material on the component. The electrically conductive conformal layer is electrically isolated from the component by the electrically insulating material on the component.