Flip-Chip Packaging Barrier Layer Solder Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flip-chip packaging methods result in undesirable performance due to solder layer collapse and short circuits caused by the flow of solder material during the reflow-soldering process, leading to large radial dimensions and adjacent solder layer connections.
Innovation Solution
A packaging structure that includes conductive connection pillars with a barrier layer on the carrier plate to prevent solder material flow, featuring solder pillars with a specific radial dimension ratio and a second barrier layer to control solder layer formation, ensuring uniformity and preventing collapse and short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing flip-chip method is used, then chip bonding is achieved, but solder layer collapse and short circuits occur due to solder material flow
Solution Approach 1:
A barrier layer is introduced as an intermediary between the solder layer and the carrier plate. This barrier layer prevents solder material from flowing onto the carrier plate surface during reflow soldering, thereby eliminating short circuits while maintaining the bonding function.
Solution Approach 2:
The carrier plate surface is segmented into different functional zones: a first area with the barrier layer for preventing solder flow, and a second area without the barrier layer for enabling solder wettability and bonding. This spatial segmentation allows simultaneous prevention of harmful flow and maintenance of bonding function.
2Area of stationary object
If solder material is allowed to flow during reflow-soldering, then bonding area is increased, but radial dimension becomes large and adjacent solder layers connect
Solution Approach 1:
Different areas of the carrier plate are given different properties: the first area has a barrier layer that prevents solder flow to control dimensional precision, while the second area allows normal solder flow for adequate bonding area. This local differentiation resolves the contradiction between area and precision.
3Reliability
If barrier layer is added to prevent solder flow, then short circuits are prevented, but device complexity increases
Solution Approach 1:
The barrier layer serves multiple functions simultaneously: it prevents solder material flow to avoid short circuits, defines the bonding area boundary, and provides a structured platform for the packaging assembly. This multi-functionality reduces the need for additional separate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the performance of the packaging structure by preventing solder layer collapse and short circuits, reducing material usage, and enhancing electrical connection quality while maintaining cost-effectiveness.
Implementation Method 1
a barrier layer located on the surface of the carrier plate around the solder layers
Implementation Method 2
solder layers located between the carrier plate and the second surfaces
Data Source
AI summary
A packaging structure includes a semiconductor chip and conductive connection pillars. Each of the conductive connection pillars has a first surface and a second surface opposite to the first surface, and the first surfaces of the conductive connection pillars are fixed to a surface of the semiconductor chip. The packaging structure also includes a carrier plate. The carrier plate is disposed opposite to the semiconductor chip. The conductive connection pillars are located between the semiconductor chip and the carrier plate, and the second surfaces face the carrier plate. The packaging structure further includes solder layers located between the carrier plate and the second surfaces, and a barrier layer located on the surface of the carrier plate around the solder layers.