Flip-Chip Solder Structure With Barrier Layer for Non-Wetting Control

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Solution Overview

Problem

In the flip-chip soldering process, packaging substrates tend to warp when heated, leading to flatness differences between chips and substrates, causing issues like surface non-wetting due to insufficient solder and solder bridging due to excessive solder.

Innovation Solution

A semiconductor structure comprising a semiconductor substrate, a metal pad, a bump, a barrier layer with grooves, and two solder layers arranged on either side of the barrier layer, which mitigates non-wetting issues by adjusting solder distribution and preventing excessive solder flow during reflow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single solder layer is used in flip-chip soldering, then the structure is simple, but solder distribution is insufficient leading to non-wetting or solder bridging

Engineering Contradiction:
Improvesolder connection reliabilityVSAvoidsolder layer structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The single solder layer is segmented into two separate solder layers (first solder layer and second solder layer) with a barrier layer in between. This segmentation allows each solder layer to perform specific functions: the first solder layer provides initial bonding and the second solder layer ensures complete wetting and prevents bridging, thereby improving reliability while managing complexity through functional division.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A barrier layer is introduced as an intermediary between the first and second solder layers. This barrier layer acts as a mediator that controls solder flow, prevents direct contact between the two solder layers during reflow, and ensures proper solder distribution. The intermediary structure resolves the contradiction by enabling reliable solder connections through controlled interaction between the two solder layers.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If solder amount is increased to prevent non-wetting, then wetting improves, but solder bridging between blocks occurs

Engineering Contradiction:
Improvewetting qualityVSAvoidsolder bridging
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The solder is divided into two separate layers with a barrier layer between them. The first solder layer is applied in controlled amounts for initial bonding, while the second solder layer is applied separately to ensure complete wetting. This segmentation prevents excessive solder from flowing between blocks, eliminating the solder bridging problem while maintaining good wetting quality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The barrier layer serves as an intermediary that physically separates the two solder layers and controls their interaction. It prevents solder from the first layer from mixing with solder from the second layer, thereby controlling solder distribution and preventing bridging while ensuring adequate solder is available for proper wetting of the bump and substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If packaging substrate is heated during flip-chip soldering, then solder reflow occurs, but substrate warping and flatness difference occur

Engineering Contradiction:
Improvesolder bonding strengthVSAvoidsubstrate flatness
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The first solder layer is applied and partially cured before the final reflow process. This preliminary action creates an initial bonding layer that helps stabilize the substrate-bump assembly, reducing the impact of thermal expansion and warping during the subsequent heating and reflow process, thereby maintaining substrate flatness while achieving reliable solder bonding.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11855032B2Semiconductor structure and manufacturing method thereof
Publication Date: 2023.12.26 CHANGXIN MEMORY TECH INC
  • US11855032B2 patent drawing
  • US11855032B2 patent drawing
  • US11855032B2 patent drawing

AI summary

The disclosed semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.