Flip-Chip Solder Structure With Barrier Layer for Warpage

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Solution Overview

Problem

In the flip-chip soldering process, packaging substrates tend to warp, leading to flatness issues between chips and substrates, causing non-wetting due to insufficient solder or solder bridging due to excessive solder, which affects the electrical performance and reliability of semiconductor structures.

Innovation Solution

A semiconductor structure and manufacturing method involving a semiconductor substrate with a metal pad, a bump, a first solder layer, a barrier layer with semi-closed grooves, and a second solder layer, where the second solder layer is positioned in the first groove and protrudes from it, and the first solder layer is in the second groove, preventing solder diffusion and bridging by blocking solder flow during reflow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional flip-chip soldering process is used, then chip interconnection can be achieved, but substrate warping occurs causing flatness differences between chip and substrate

Engineering Contradiction:
Improveelectrical performanceVSAvoidflatness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The solder layer is segmented into multiple independent solder masses arranged in an array, with each solder mass confined by sidewall spacers. This segmentation prevents solder diffusion and bridging while ensuring adequate solder coverage for reliable electrical connection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Sidewall spacers are introduced as intermediary structures formed on the sidewalls of solder masses. These spacers act as physical barriers that prevent solder creep and bridging between adjacent blocks, while allowing the solder to maintain adequate coverage for wetting.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If insufficient solder is used, then substrate warping is reduced, but non-wetting occurs due to solder creep

Engineering Contradiction:
ImproveflatnessVSAvoidwetting
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

Sidewall spacers are formed preliminarily on the sidewalls of solder masses before the soldering process. This preliminary action prevents solder creep during reflow, ensuring that solder remains within designated areas and maintains adequate coverage for wetting without requiring excessive solder quantity.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If excessive solder is used, then wetting is improved, but solder bridging between blocks occurs

Engineering Contradiction:
ImprovewettingVSAvoidsolder placement precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The solder layer is divided into discrete solder masses separated by sidewall spacers. This segmentation allows adequate solder quantity for wetting within each block while preventing solder diffusion to adjacent blocks, eliminating bridging issues.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Sidewall spacers serve as intermediary barrier structures that physically confine solder masses. These spacers enable the use of sufficient solder for reliable wetting while preventing solder creep and bridging between adjacent interconnection blocks.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Reliability

If solder mass is increased to prevent non-wetting, then wetting is improved, but solder bridging between blocks occurs

Engineering Contradiction:
ImprovewettingVSAvoidsolder bridging
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Sidewall spacers are introduced as intermediary barrier structures that enable the use of adequate solder mass for reliable wetting while preventing solder diffusion to adjacent blocks. The spacers act as physical boundaries that eliminate bridging while allowing sufficient solder volume for proper wetting.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3940772B1Semiconductor structure and manufacturing method therefor
Publication Date: 2024.07.17 CHANGXIN MEMORY TECH INC
  • EP3940772B1 patent drawingFigure 1~2
  • EP3940772B1 patent drawingFigure 3~4
  • EP3940772B1 patent drawingFigure 5~6

AI summary

The present disclosure relates to the field of semiconductor technology, and discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is arranged on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is arranged on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the solder layer can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.