Flip-Chip Bonding Openings That Prevent Misalignment and Solder Overflow
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Solution Overview
Problem
The challenge in semiconductor chip packaging is the misalignment or inclination during flip-chip bonding, leading to poor bonding due to deviated thermal pressure or non-uniform pressure distribution during thermo compression bonding.
Innovation Solution
A semiconductor structure and forming method involving the formation of up-narrow and down-wide openings in a covering film on the substrate, which correspondingly expose metal pads, allowing solder bumps on metal pillars to be precisely located and filled, preventing misalignment and ensuring firm bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flip-chip bonding is performed with conventional flat surfaces, then bonding process is simple, but misalignment and inclination occur causing poor bonding reliability
Solution Approach 1:
The patent applies asymmetry by creating non-planar surfaces with protrusions and recesses that interlock during bonding. The first surface has protrusions while the second surface has corresponding recesses, forming an asymmetric complementary structure that prevents misalignment and inclination, thereby improving bonding reliability without excessive complexity
Solution Approach 2:
The patent implements preliminary action by pre-forming the protrusions and recesses on the bonding surfaces before the actual bonding process. This advance preparation of complementary geometric features ensures proper alignment and contact during bonding, preventing misalignment issues without adding complexity to the bonding process itself
2Productivity
If higher packaging density is achieved, then more interconnections are needed, but misalignment and inclination cause poor bonding
Solution Approach 1:
The asymmetric protrusion-recess structure provides self-aligning features that become increasingly important as packaging density increases. The complementary shapes guide precise positioning even when dealing with finer pitch interconnections, maintaining bonding reliability despite higher packaging demands
Solution Approach 2:
By pre-forming the complementary geometric features on high-density interconnection structures, the patent ensures that even as packaging density increases and feature sizes decrease, the self-aligning properties maintain bonding reliability through the preliminary established geometric constraints
3Ease of manufacture
If conventional bonding surfaces are used, then manufacturing is simple, but thermal pressure is non-uniform causing misalignment
Solution Approach 1:
The asymmetric protrusion-recess structure creates inherent mechanical constraints that maintain alignment precision during bonding. The interlocking geometry ensures uniform thermal pressure distribution by preventing inclination, achieving manufacturing precision without significantly complicating the manufacturing process
Solution Approach 2:
The preliminary formation of complementary geometric features establishes precise alignment constraints before bonding occurs. This advance structuring ensures that during the bonding process, thermal pressure is distributed uniformly across the contact surfaces, maintaining alignment precision while keeping the bonding process itself relatively simple
Data Source
AI summary
The present application provides a semiconductor structure and a forming method thereof. The method of forming the semiconductor structure includes: providing a semiconductor chip and a substrate; forming, on the substrate, a first covering film covering a metal pad and a surface of the substrate, a plurality of up-narrow and down-wide openings being formed in the first covering film, and a bottom of each of the up-narrow and down-wide openings correspondingly exposing a surface of the metal pad; and flipping the semiconductor chip onto the substrate, such that a solder bump on a metal pillar is correspondingly located in the up-narrow and down-wide opening, and the solder bump fill the up-narrow and down-wide opening.