Flip Chip Carrier Bonding Portions for Solder Yield

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional gold-tin flip chip package structures experience poor bonding due to irregular solder bulges away from the bumps, leading to reduced yield and inconsistent solder distribution.

Innovation Solution

A carrier with a patterned trace layer featuring outward protruding bonding portions with a larger line width than the traces, arranged along a straight line, to ensure consistent solder consolidation and bonding with the bumps during the reflow process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the opening of the solder mask is designed to be larger than the chip to facilitate underfill filling, then the ease of manufacture is improved, but the circuit length becomes longer causing solder to consolidate and bulge irregularly due to cohesive force, worsening the manufacturing precision

Engineering Contradiction:
Improveunderfill fillingVSAvoidsolder bulge position
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The bonding portion is designed with a larger line width specifically at the location where solder should consolidate, creating a local quality difference. This wider bonding portion acts as a designated consolidation zone that guides solder to bulge at the correct position, while other parts of the circuit maintain normal width. This resolves the contradiction by providing local structural optimization without changing the overall solder mask opening size.

Inventive Principle:
Principle #3Local quality

2Device complexity

If solder consolidates and bulges irregularly due to longer circuit length and cohesive force, then the device complexity remains the same, but the reliability deteriorates due to poor bonding between gold and tin

Engineering Contradiction:
Improvecircuit structureVSAvoidgold-tin bonding
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The bonding portion is pre-designed with a larger line width before the reflow process, creating a predetermined consolidation zone. This preliminary structural design ensures that during the reflow process, solder will naturally consolidate at the bonding portion due to its larger area, preventing irregular bulging and ensuring reliable gold-tin bonding. The structure is prepared in advance to guide the solder behavior during processing.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If the bonding portion is designed with a larger line width than the trace, then the manufacturing precision of solder placement is improved, but the device complexity increases due to the patterned trace layer design

Engineering Contradiction:
Improvesolder consolidation positionVSAvoidpatterned trace layer
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The bonding portion is merged with the trace to form an integrated cross-shaped structure. Instead of being a separate component, the bonding portion is directly combined with the trace layer, creating a unified structure that serves both as a electrical connection path and a solder consolidation zone. This merging reduces the need for additional separate structures while achieving the precision solder placement goal.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design ensures precise solder bonding with the bumps, increasing the yield of the flip chip package structure by maintaining solder bulges at consistent positions, thus improving the reliability of the gold-tin bonding.

Implementation Method 1

the pre-solders are disposed on the bonding portions, respectively

Methodology Applied
Scientific EffectSoldering: Soldering

Data Source

PatentUS7791211B2Flip chip package structure and carrier thereof
Publication Date: 2010.09.07 ADVANCED SEMICON ENG INC
  • US7791211B2 patent drawing
  • US7791211B2 patent drawing
  • US7791211B2 patent drawing

AI summary

A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has a carrying surface and a patterned trace layer thereon. The patterned trace layer has a plurality of traces, and each of the traces has an outward protruding bonding portion corresponding to the bump. The line width of the bonding portion is greater than that of the trace. The pre-solders are disposed on the bonding portions, respectively. The bumps are disposed between the bump pads and the corresponding pre-solders such that the chip is electrically connected to the carrier through the bumps.