Flip Chip Package Buffer Layer for CTE Stress and EMI Shielding

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Solution Overview

Problem

Conventional flip chip packages experience high stresses due to mismatched coefficients of thermal expansion (CTE) of different materials, leading to failures such as delamination and cracking.

Innovation Solution

Incorporation of a die attach film layer with a coefficient of thermal expansion between 30 ppm/C and 35 ppm/C and a Young's modulus of 4 GPa to 5 GPa, acting as a stress buffer between chiplet, underfill, and epoxy molding, along with an electromagnetic interference (EMI) coating for protection and uniform stiffness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If conventional flip chip packages are used, then smaller form factor and reduced inductance are achieved, but higher stresses occur due to CTE mismatch between different materials

Engineering Contradiction:
Improveform factorVSAvoidinternal stress
Core Design Contradiction:
Volume of moving objectVSStress or pressure

Solution Approach 1:

A die attach film layer is introduced as an intermediary material between the chiplet and the epoxy molding compound. This intermediate layer has a coefficient of thermal expansion (CTE) of 30-35 ppm/°C and a Young's modulus of 4-5 GPa, which serves as a stress buffer to accommodate CTE mismatches between the silicon chiplet (CTE ~2.6 ppm/°C) and the epoxy molding compound, thereby reducing internal stresses while maintaining the flip chip package's compact form factor

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs a composite material structure consisting of multiple layers with different mechanical and thermal properties. The die attach film layer is a composite material designed with specific CTE (30-35 ppm/°C) and Young's modulus (4-5 GPa) characteristics that differ from both the chiplet and the epoxy molding compound, creating a gradient structure that gradually transitions between materials with vastly different CTE values, thus reducing stress concentration

Inventive Principle:
Principle #40Composite materials

2Strength

If conventional flip chip packages are used, then direct mounting and heat conduction are improved, but package failures occur due to stress-induced delamination and cracking

Engineering Contradiction:
Improveheat conductionVSAvoidpackage reliability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The die attach film layer acts as a pre-configured cushioning layer that anticipates and absorbs thermal expansion stresses before they can cause damage. By positioning this compliant layer (Young's modulus 4-5 GPa) between the rigid chiplet and the epoxy molding compound, the structure pre-accommodates CTE mismatches during temperature cycling, preventing stress-induced delamination and cracking that would otherwise compromise package reliability

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent changes the mechanical parameters of the interface between chiplet and epoxy molding by introducing a layer with specifically controlled Young's modulus (4-5 GPa) and CTE (30-35 ppm/°C). This parameter modification creates a more compliant interface that can deform elastically under thermal stress, preventing the rigid stress transfer that leads to delamination and cracking, thereby improving reliability while maintaining effective heat conduction paths

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces stress caused by CTE mismatch, preventing failures like delamination and cracking, while providing EMI protection and maintaining structural integrity.

Implementation Method 1

Distinguished flip chip packaging for stress relaxation and enhanced em protection

Methodology Applied
Scientific EffectStress relaxation: Stress Relaxation

Data Source

PatentUS20250259907A1Distinguished flip chip packaging for stress relaxation and enhanced em protection
Publication Date: 2025.08.14 APPLIED MATERIALS INC
  • US20250259907A1 patent drawing
  • US20250259907A1 patent drawing
  • US20250259907A1 patent drawing

AI summary

Exemplary flip chip packages may include a carrier substrate. The packages may include a chiplet electrically and physically coupled with the carrier substrate via a plurality of interconnects. The packages may include an underfill positioned between the carrier substrate and the chiplet. The packages may include an epoxy molding coupled with the carrier substrate and covering an exposed surface of the chiplet. The packages may include a die attach film layer positioned about the chiplet. The die attach film layer may extend between and separates the chiplet and the carrier substrate. The die attach film layer may extend between and separates the chiplet and the epoxy molding. The die attach film layer may have a coefficient of thermal expansion of between 30 ppm/C and 35 ppm/C, inclusive. The die attach film layer may have a Young's modulus of between 4 GPa and 5 GPa, inclusive.