Flip Chip Bump Fabrication via Patterned Buildup and Flash Plating
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Solution Overview
Problem
Existing flip chip bump formation methods, such as Solder On Pad (SOP) processes, face limitations in forming reliable bumps on high-density substrates due to issues with small bump pitch, leading to unreliable solder screen processes and shorting problems.
Innovation Solution
A method involving the formation of a patterned buildup layer, flash plating a conductor layer, and creating patterned upper resist with flip chip bump openings to fill and define flip chip bumps, allowing for extremely small pitch formation suitable for high-density substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If solder screen process is used to apply solder paste directly to pads, then the process is simple and cost-effective, but the bump pitch cannot be made small enough for high-density substrates
Solution Approach 1:
The patent divides the bump formation process into multiple sequential steps: forming openings in the dielectric layer, depositing conductor material, forming a solder resist layer with openings, and applying solder paste. This segmentation allows each step to be optimized independently, enabling small bump pitch while maintaining process reliability.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the conductor layer and solder resist layer before applying solder paste. The conductor layer is deposited and patterned in advance, and the solder resist layer is formed with precisely positioned openings, ensuring accurate bump placement at small pitches without requiring complex real-time alignment.
2Productivity
If bump pitch is reduced for high-density substrates, then substrate density increases, but solder screen process becomes unreliable and causes shorting
Solution Approach 1:
The patent introduces a solder resist layer as an intermediary between the conductor layer and the solder paste. This intermediate layer with precisely formed openings ensures that solder paste is applied only at the correct locations, preventing shorting between adjacent bumps while enabling high substrate density through small pitch.
Solution Approach 2:
The patent applies local quality by creating openings in the solder resist layer only at specific locations where bumps are needed. This localized approach ensures precise solder placement at each bump site while maintaining isolation between adjacent bumps, enabling reliable high-density interconnections.
3Area of stationary object
If solder mask openings are made small for small pads, then pad size is reduced for high-density substrates, but solder screen process cannot reliably fill the openings
Solution Approach 1:
The patent performs preliminary action by pre-forming openings in the solder resist layer that are precisely sized and positioned. These pre-formed openings guide the solder paste application process, ensuring reliable filling even when the openings are small, thereby maintaining pad size reduction for high-density substrates while ensuring manufacturing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables reliable formation of flip chip bumps with extremely small pitch, effectively addressing the limitations of existing technologies for high-density substrate applications by ensuring accurate and consistent bump formation.
Implementation Method 1
A conductor layer is flash plated on the patterned buildup layer and within the patterned buildup layer opening
Data Source
AI summary
A method includes forming a patterned buildup layer on a first surface of a dielectric layer, the patterned buildup layer including a patterned buildup layer opening exposing a trace coupled to the dielectric layer. A conductor layer is flash plated on the patterned buildup layer and within the patterned buildup layer opening. The patterned buildup layer opening is filled with a blanket conductive filler layer. The blanket conductive filler layer and the conductor layer are planarized to form a flip chip bump.