Flip Chip Cavity Package With Molded Leadframe
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high I/O counts while maintaining reliability and resisting moisture, as Chip Scale Packages require wider pitches and are prone to 'popcorn' effects due to moisture ingress in Ball Grid Array packages.
Innovation Solution
A process involving a molded leadframe strip with flip chip semiconductor devices and conductive masses, encapsulated in a mold compound to form a cavity, allowing for robust electrical interconnection and moisture resistance, with optional dual leadframes and soft metal coupling for increased flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Ball Grid Array packages are used to achieve high I/O counts, then the number of I/O increases, but moisture ingress causes popcorn effects and reliability decreases
Solution Approach 1:
The patent extracts the semiconductor die from the traditional package structure and mounts it directly onto the leadframe in a flip-chip configuration. This eliminates the need for a separate package body that would otherwise trap moisture, while still providing high I/O counts through the ball grid array structure.
Solution Approach 2:
The patent applies a conformal coating or encapsulant material over the mounted die and conductive structures to create a protective barrier against moisture ingress. This inert environment prevents moisture from reaching sensitive internal structures, eliminating the popcorn effect while maintaining high I/O reliability.
2Volume of moving object
If Chip Scale Packages are used to reduce package size, then package size decreases, but pitch must be widened which increases die size and cost
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional flip-chip mounting with vertical conductive structures. This dimensional change allows for much finer pitch dimensions since the electrical connections are made vertically through the die thickness rather than laterally across the surface, enabling smaller package sizes without compromising manufacturing precision.
3Speed
If package size is reduced to match die size, then bandwidth and latency improve, but the package becomes insufficient to support the number of leads required
Solution Approach 1:
The patent nests multiple functional elements within a compact structure: the die is mounted face-down on the leadframe, conductive structures are embedded within the mold compound, and the entire assembly is enclosed in a protective package body. This nested arrangement maximizes the number of supported leads within a minimal footprint, achieving both high I/O counts and fast signal speeds.
Data Source
AI summary
A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound. The second mold compound can be molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed or molded to produce a globular form on the flip chip semiconductor device. The molded leadframe strip is singulated to form discrete semiconductor packages.