Flip Chip CMOS on Passive Substrate Grounding
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Solution Overview
Problem
Current semiconductor integration schemes using wire bonds and through wafer/silicon vias result in high inductance, poor thermal properties, and inflexible design, leading to increased costs and complexity, especially as CMOS devices advance through technology nodes.
Innovation Solution
Implementing an integrated passive device chip with through wafer vias mounted to a ground plane, using flip chip technology to mount CMOS devices, which reduces inductance and thermal issues while allowing for flexible design scaling across multiple CMOS technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect CMOS chips to signal lines, then electrical connections are established, but inductance and resistance increase
Solution Approach 1:
The patent extracts the wire bond connection method and replaces it with direct chip-to-substrate bonding. By removing the intermediate wire bond element, the inductance and resistance associated with long wire leads are eliminated, achieving lower parasitic values while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from perimeter-based wire bond connections to area-based flip-chip bonding. By mounting bond pads across the entire chip surface rather than only at the perimeter, the connection path is dramatically shortened, reducing inductance and resistance in three-dimensional space.
2Reliability
If wire bonds are used for connecting CMOS devices, then electrical connections are made, but thermal properties deteriorate
Solution Approach 1:
The patent merges the electrical connection function and thermal dissipation function into a single integrated structure. The same bonding pads and interconnect structures that provide electrical connectivity also serve as heat conduction paths, eliminating the thermal inefficiencies of wire bonds while maintaining electrical performance.
3Reliability
If bond pads are placed on the perimeter of CMOS chips for wire bond connections, then electrical connections are established, but valuable chip area is wasted
Solution Approach 1:
The patent moves bond pads from the two-dimensional perimeter to the three-dimensional chip surface, distributing them across the entire active area. This allows bond pads to be positioned optimally for both electrical connection and area utilization, transforming the connection architecture from edge-based to surface-based.
4Reliability
If through wafer/silicon vias are used in CMOS chips for grounding, then grounding connections are established, but design flexibility decreases across technology nodes
Solution Approach 1:
The patent extracts the through-wafer via requirement from the CMOS chip design and relocates it to the substrate level. By implementing grounding vias in the substrate rather than the CMOS chip itself, the chip design becomes technology-node-agnostic, allowing CMOS processes to evolve without being constrained by via redesign requirements.
5Reliability
If through wafer/silicon vias are propagated across multiple CMOS technology nodes, then grounding is maintained, but design and manufacturing costs increase
Solution Approach 1:
The patent segments the grounding structure into two independent parts: substrate-level vias and chip-level connections. By separating these functions, the substrate vias can be designed once and reused across multiple CMOS technology nodes, while the chip designs can evolve independently, significantly reducing cumulative design and manufacturing costs.
Data Source
AI summary
Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.