Semiconductor Flip-Chip Package With Conductive Pillars
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Solution Overview
Problem
Existing semiconductor flip-chip packages face challenges in achieving low parasitic inductances and capacitances with short interconnects, which are crucial for excellent electrical performance and small form factor.
Innovation Solution
The method involves using a molded interconnect substrate (MIS) or leadframe with conductive pillars formed on the substrate, connecting semiconductor dies with contact pads to these pillars, and applying an encapsulant to create a stable and efficient interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip-chip mounting is used with solder bumps deposited on die pads, then electrical performance is improved, but interconnect length cannot be sufficiently reduced
Solution Approach 1:
Instead of depositing solder bumps on the die pads (conventional approach), the patent inverts the process by forming conductive pillars on the substrate and then attaching the die with contact pads that connect to these pillars. This inversion allows the interconnect path to be significantly shortened as the connection is made directly from the contact pad to the pillar without requiring long solder bumps extending from the die surface.
Solution Approach 2:
The patent transitions from a planar interconnect structure (solder bumps on die surface) to a three-dimensional structure with conductive pillars extending vertically from the substrate. This dimensional change enables shorter interconnect paths by utilizing the vertical dimension for direct connection between the die contact pads and the substrate conductive structures.
2Reliability
If conventional flip-chip mounting is used, then electrical performance is improved, but parasitic inductances and capacitances cannot be sufficiently reduced
Solution Approach 1:
By inverting the conventional approach and forming conductive pillars on the substrate rather than solder bumps on the die, the patent minimizes the interconnect path length. This directly reduces the loop area for current flow, thereby reducing parasitic inductances and capacitances while maintaining excellent electrical performance.
Solution Approach 2:
The patent changes the geometric parameters of the interconnect structure by using short, thick conductive pillars instead of long, thin solder bumps. This parameter change reduces the surface area for parasitic capacitance and minimizes the inductive loop area, thereby reducing harmful parasitic effects.
3Volume of moving object
If conventional flip-chip mounting is used, then small form factor is achieved, but the form factor cannot be sufficiently minimized
Solution Approach 1:
The inverted approach of forming conductive pillars on the substrate allows for extremely short interconnect lengths, which directly contributes to minimizing the overall package form factor. The short distance between contact pads and pillars enables compact packaging while maintaining electrical performance.
Solution Approach 2:
By utilizing vertical conductive pillars instead of horizontal solder bumps, the patent effectively moves the interconnect path into the vertical dimension, reducing the horizontal footprint and thereby minimizing the overall form factor of the packaged device.
Data Source
AI summary
A semiconductor flip-chip package includes a substrate having a first main face, a second main face opposite to the first main face, and one or more conductive structures disposed on the first main face, one or more pillars disposed on at least one of the conductive structures, a semiconductor die having one or more contact pads on a main face thereof, the semiconductor die being connected to the substrate so that at least one of the contact pads is connected with one of the pillars, and an encapsulant disposed on the substrate and the semiconductor die.