Flip-Chip Die Attach Conductive Members for Co-Planarity Control
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Solution Overview
Problem
The existing flip-chip package manufacturing techniques, such as electroplating and subsequent reflow, result in unevenly-sized conductive members, leading to co-planarity issues and high manufacturing costs due to multiple expensive and time-consuming photolithography, plating, and etching steps, while also being prone to electromigration, especially with shrinking die sizes.
Innovation Solution
The method involves pre-forming conductive members and using a flux adhesive material to hold them in place, eliminating the need for photolithography, plating, and etching steps, and reflowing the conductive members for die attach to conductive terminals, thereby reducing manufacturing complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electroplating and reflow techniques are used to form conductive members, then conductive members can be created for die attach, but the conductive members become unevenly-sized leading to co-planarity issues
Solution Approach 1:
The conductive members are pre-formed on the die before flip-chip attachment, eliminating the need for subsequent plating and etching steps. This preliminary formation ensures uniform size and shape, resolving the co-planarity issues that arise from post-formation electroplating processes.
Solution Approach 2:
The patent extracts and eliminates the problematic photolithography, plating, and etching steps from the manufacturing process. By removing these complex sequential operations, the invention achieves uniform conductive members without the co-planarity defects caused by electroplating variability.
2Ease of manufacture
If multiple photolithography, plating, and etching steps are used to form conductive members, then conductive members can be created, but manufacturing costs increase and cycle time extends
Solution Approach 1:
The invention merges the formation of conductive members with the die fabrication process itself, integrating conductive member creation into the existing semiconductor manufacturing flow. This consolidation eliminates the need for separate photolithography, plating, and etching steps, thereby reducing both manufacturing complexity and cycle time.
Solution Approach 2:
Conductive members are formed as part of the preliminary die fabrication process rather than as a separate subsequent step. This preliminary action approach allows conductive members to be created during standard manufacturing operations, eliminating the need for additional expensive and time-consuming processing steps.
3Reliability
If conventional electroplating processes are used, then conductive members can be formed, but electromigration issues arise especially with shrinking die sizes
Solution Approach 1:
The invention changes the material parameters and formation method of conductive members, using materials and processes that inherently resist electromigration. By altering how conductive members are formed and what materials are used, the patent achieves reliable electrical connections even as die sizes shrink and current densities increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates co-planarity challenges and reduces manufacturing cycle times, lowering package costs while minimizing electromigration concerns by simplifying the manufacturing process and maintaining effective die attach.
Implementation Method 1
a flux adhesive material coupled to the conductive pillar
Implementation Method 2
reflowing the conductive member; coupling the reflowed conductive member to a conductive terminal using a reflow technique, thereby producing a solder layer
Data Source
AI summary
In examples, a semiconductor package comprises a semiconductor die having an active surface; a conductive layer coupled to the active surface; and a polyimide layer coupled to the conductive layer. The package also comprises a conductive pillar coupled to the conductive layer and to the polyimide layer; a flux adhesive material coupled to the conductive pillar; and a solder layer coupled to the flux adhesive material. The package further includes a conductive terminal coupled to the solder layer and exposed to a surface of the package, the active surface of the semiconductor die facing the conductive terminal.